Spike Generation Circuit With Delay Control for Low-Power Pulses
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Solution Overview
Problem
Spike generator circuits, such as those used in neural networks, face challenges in reducing power consumption while maintaining efficient spike signal generation.
Innovation Solution
The proposed spike generation circuit incorporates a CMOS inverter, a switch, an inverting circuit, and a delay circuit, with specific configurations of CMOS inverters and capacitance elements to control signal inversion and delay, resulting in a spike signal with a narrow pulse width and reduced power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If conventional spike generator circuits are used, then spike signal generation is achieved, but power consumption is high
Solution Approach 1:
The circuit uses periodic switching action where the switch element operates in discrete on/off cycles controlled by the delay circuit, enabling spike signal generation only when necessary rather than continuous operation, thereby reducing power consumption while maintaining signal generation capability
Solution Approach 2:
The delay circuit performs preliminary timing action by delaying the control signal before it reaches the switch element, allowing the circuit to prepare and trigger spike signals at precisely controlled intervals, ensuring efficient signal generation with minimal power expenditure
2Use of energy by moving object
If the pulse width of spike signals is reduced, then power consumption decreases, but signal transition steepness becomes difficult to maintain
Solution Approach 1:
The circuit dynamically adjusts the switch element's state between fully on and fully off conditions, creating rapid transitions that produce steep signal edges. The delay circuit dynamically controls the timing duration, enabling narrow pulse widths while maintaining transition steepness through optimized switching dynamics
Solution Approach 2:
The circuit changes the temporal parameter of the control signal through the delay circuit, transforming a broader input signal into a narrow pulse output. This parameter transformation enables short pulse widths with steep transitions by precisely controlling the duration and timing of the switch element's active state
Data Source
AI summary
A spike generation circuit includes a first CMOS inverter connected between a first power supply and a second power supply, an output node of the first CMOS inverter being coupled to a first node that is an intermediate node coupled to an input terminal to which an input signal is input, a switch connected in series with the first CMOS inverter, between the first power supply and the second power supply, a first inverting circuit that outputs an inversion signal of a signal of the first node to a control terminal of the switch, and a delay circuit that delays the signal of the first node, outputs a delayed signal to an input node of the first CMOS inverter, and outputs an isolated output spike signal to an output terminal.