Spike Domain Neural Processor Timing Encoding
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Solution Overview
Problem
Existing signal processing systems face limitations in accuracy due to dynamic range constraints in analog domains and introduce quantization noise in digital domains, particularly when handling real-time non-linear processing of input signals from RF or hyperspectral sensors.
Innovation Solution
A neural network architecture utilizing interconnected processors that operate in either the spike or pulse domain, employing 1-bit DACs for internal feedback loops, hysteresis quantizers, and integrators to encode information in timing without amplitude quantization, thereby avoiding accuracy limitations and quantization noise.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If analog feedback amplifiers are used for signal processing, then the system can perform non-linear processing, but accuracy is severely limited by dynamic range constraints
Solution Approach 1:
The patent replaces analog feedback amplifiers with a hybrid spiking-pulse domain system that uses 1-bit DACs and digital logic circuits. This substitution eliminates the need for high-precision analog components while maintaining non-linear processing capabilities through the spiking neural network architecture, thereby resolving the contradiction between versatility and precision.
Solution Approach 2:
The invention changes the domain of signal representation from continuous analog values to discrete spiking/pulse events with timing encoding. This parameter transformation allows the system to achieve high precision through timing resolution rather than amplitude resolution, enabling accurate non-linear processing without dynamic range limitations.
2Ease of operation
If traditional ADC conversion is used to digitize signals, then digital processing can be performed, but speed is limited by ADC conversion performance and quantization noise is introduced
Solution Approach 1:
The patent extracts the essential information from analog signals by encoding it in the timing of spiking events rather than converting the full analog waveform through traditional ADC. This extraction approach eliminates the speed bottleneck of ADC conversion while preserving the ability to perform digital processing on the extracted features.
Solution Approach 2:
The spiking neural network acts as an intermediary between analog sensors and digital processing circuits. The spiking events serve as a compact representation that can be generated directly from analog inputs without full ADC conversion, enabling fast feature extraction while maintaining digital processing capabilities.
3Reliability
If timing gates are used in digital circuits, then signal timing can be controlled, but quantization noise is introduced due to amplitude and timing quantization
Solution Approach 1:
Instead of using timing gates to control and quantize signals, the patent inverts the approach by using continuously timed spiking events to carry information. The timing precision is maintained through the natural timing resolution of the spiking mechanism rather than through gate-based quantization, eliminating quantization noise while preserving timing control.
4Area of stationary object
If compact VLSI implementation is pursued, then device area is reduced, but analog component precision requirements increase
Solution Approach 1:
The patent employs 1-bit DACs and simple digital logic circuits that are inherently more compact and easier to manufacture with standard precision than high-precision analog components. These simpler components can be densely integrated in VLSI technology, achieving compact implementation without requiring high manufacturing precision.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enables fast feature extraction in real-time without quantization noise, with compact implementation suitable for VLSI technology, and allows for high-speed processing of analog signals without the need for analog feedback amplifiers or timing gates.
Implementation Method 1
The circuits of this invention do not require any analog feedback amplifiers. Simple 1 bit DACs (Digital to Analog Converters) are used in all the internal feedback loops.
Implementation Method 2
Each elementary circuit is composed of DACs, integrators, hysteresis quantizers, delay elements and simple asynchronous logical gates.
Implementation Method 3
Simple 1 bit DACs (Digital to Analog Converters) are used in all the internal feedback loops.
Data Source
AI summary
A neural network has an array of interconnected processors, each processor operating either the pulse domain or spike domain. Each processor has (i) first inputs selectively coupled to other processors in the array of processors, each first input having an associated 1 bit DAC coupled to a summing node, (ii) second inputs selectively coupled to inputs of the neural network, the second inputs having current generators associated therewith coupled to said summing node, (iii) a filter/integrator for generating an analog signal corresponding to current arriving at the summing node, (iv) an optional nonlinear element coupled to the filter/integrator, and (v) an analog-to-pulse converter, if the processors operate in the pulse domain, or an analog-to-spike convertor, if the processors operate in the spike domain, for converting an analog signal output by the optional nonlinear element or by the filter/integrator to either the pulse domain or spike domain, and providing the converted analog signal as an unquantized pulse or spike domain signal at an output of the processor. The array of processors are selectively interconnected with either unquantized pulse domain or spike domain signals.