Spike Neural Network Circuit for Parasitic Charge Correction
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Solution Overview
Problem
The accumulation of electric charges in a membrane capacitor of a spike neural network (SNN) circuit due to parasitic capacitance leads to errors and performance degradation.
Innovation Solution
The SNN circuit includes a spike generator that converts input spike signals into sub-spike and main spike signals, a synaptic circuit with a potential correction circuit to control the voltage of parasitic capacitance, and a transistor to manage signal delivery to the membrane capacitor, minimizing charge errors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a voltage or charge is supplied from the synaptic circuit and accumulated in a membrane capacitor of the neuron circuit, then the neuron can fire when the voltage exceeds a threshold voltage, but due to the supply of electric charges by parasitic capacitance included in the synaptic circuit, an error occurs in the amount of charges accumulated in the membrane capacitor
Solution Approach 1:
The patent extracts the harmful parasitic capacitance effect from the synaptic circuit by separating the charge accumulation function into a dedicated membrane capacitor. The synaptic circuit generates the operation signal based on weight, while the membrane capacitor independently accumulates this signal, isolating the parasitic capacitance effects to minimize their impact on accuracy.
Solution Approach 2:
The patent introduces a transistor as an intermediary component between the synaptic circuit and the membrane capacitor. The transistor controls the delivery of the operation signal to the membrane capacitor, acting as a mediator that prevents direct coupling of parasitic capacitance from the synaptic circuit to the membrane capacitor, thereby reducing charge accumulation errors.
2Speed
If the synaptic circuit directly connects to the membrane capacitor to deliver the operation signal, then the signal transmission is simple and fast, but the parasitic capacitance in the synaptic circuit causes charge over-accumulation and errors in the membrane capacitor
Solution Approach 1:
The transistor serves as an intermediary that enables fast signal transmission while maintaining precision. It rapidly switches between conducting and non-conducting states to deliver the operation signal to the membrane capacitor when needed, while blocking the parasitic capacitance effects, thus achieving both speed and precision requirements.
Solution Approach 2:
The transistor provides dynamic control over the signal delivery process. By dynamically switching its conducting state based on the spike signal timing, it allows the operation signal to be delivered quickly when required while preventing parasitic charge accumulation, thereby achieving both fast transmission and high precision.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach minimizes charge over-accumulation in the membrane capacitor, reducing errors and enhancing the performance and accuracy of the SNN circuit.
Implementation Method 1
when a voltage or charge supplied from the synaptic circuit is accumulated in a membrane capacitor of the neuron circuit and the voltage exceeds a threshold voltage, a neuron fires
Implementation Method 2
due to the supply of electric charges by parasitic capacitance included in the synaptic circuit, an error may occur in the amount of charges accumulated in the membrane capacitor
Data Source
AI summary
Disclosed is an SNN circuit including a spike generator that receives an input spike signal and converts the input spike signal into a sub-spike signal and a main spike signal, a synaptic circuit that generates an operation signal based on a weight and outputs the operation signal in response to the main spike signal, a membrane capacitor that accumulates the operation signal, and a potential correction circuit that corrects an output terminal voltage of the synaptic circuit based on a voltage of the membrane capacitor.