Spike Neural Network Synapse Circuit Area Reduction

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Solution Overview

Problem

The existing spike neural network circuits face challenges in reducing the area of the synaptic circuit while maintaining high-precision calculations, leading to excessively large transistors in the current source array.

Innovation Solution

The proposed spike neural network circuit employs a pulse generator that generates first and second modulation pulses based on an input spike signal, with current sources activated for different durations to accumulate signals in a membrane capacitor, allowing for a more compact design by optimizing the channel width of transistors and adjusting the duration of current source activation based on binary weight bits.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If transistors in the current source array are made larger to achieve high-precision calculation, then calculation precision is improved, but the area of the synapse circuit increases

Engineering Contradiction:
Improvecalculation precisionVSAvoidsynapse circuit area
Core Design Contradiction:
Measurement precisionVSArea of stationary object

Solution Approach 1:

The current source array is divided into multiple sub-arrays, each handling a portion of the weight bits. This segmentation allows each transistor to be smaller while collectively achieving the required precision through coordinated operation of multiple current sources.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The circuit employs sequential activation of current sources in the array, where different current sources are activated at different time periods corresponding to different weight bits. This time-multiplexed approach enables high-precision calculation without requiring all transistors to be large simultaneously, thus reducing overall area.

Inventive Principle:
Principle #19Periodic action

2Measurement precision

If the number of current sources in the array is increased to improve calculation precision, then calculation precision is improved, but the area of the synapse circuit increases

Engineering Contradiction:
Improvecalculation precisionVSAvoidsynapse circuit area
Core Design Contradiction:
Measurement precisionVSArea of stationary object

Solution Approach 1:

Multiple current sources are merged into a unified computational structure where they operate cooperatively. The patent combines the outputs of multiple current sources through a summation node, achieving high-precision calculation through their collective contribution rather than requiring each individual source to be oversized.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

Current sources are activated in a periodic or sequential manner corresponding to the significance of weight bits. Less significant bits use shorter activation periods with smaller current sources, while more significant bits use longer activation periods, optimizing the balance between precision and area.

Inventive Principle:
Principle #19Periodic action

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach reduces the area of the synapse circuit while maintaining high-precision calculations by optimizing transistor size and activation durations, enabling a more compact and efficient neural network implementation.

Implementation Method 1

a membrane capacitor, a first switch that delivers a first calculation signal generated from the first current source array to the membrane capacitor

Methodology Applied
Scientific EffectCapacitance: Capacitance

Implementation Method 2

the membrane capacitor may be configured to accumulate the first calculation signal during a time interval when the first modulation pulse is activated and accumulate the second calculation signal during a time interval when the second modulation pulse is activated

Methodology Applied
Scientific EffectElectrical charge accumulation: Electrical Accumulator

Data Source

PatentUS20230385620A1Spike neural network circuit
Publication Date: 2023.11.30 ELECTRONICS & TELECOMM RES INST
  • US20230385620A1 patent drawing
  • US20230385620A1 patent drawing
  • US20230385620A1 patent drawing

AI summary

Disclosed is a spike neural network circuit which includes a pulse generator that receives an input spike signal and generates a first modulation pulse and a second modulation pulse based on the input spike signal, first and second current source arrays controlled based on a weight memory, a membrane capacitor, a first switch that delivers a first calculation signal generated from the first current source array to the membrane capacitor, in response to the first modulation pulse, and a second switch that delivers a second calculation signal generated from the second current source array to the membrane capacitor, in response to the second modulation pulse.