In-Substrate Spiked Capacitor Structure for High Passive Density
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Solution Overview
Problem
Current semiconductor packaging methods face challenges in accommodating discrete passive devices due to shrinking design rules, leading to limited space for passives like capacitors, which results in increased electrical loss and reduced package functionality.
Innovation Solution
The fabrication of in-situ spiked capacitors within the substrate package by etching a conductive polymer matrix with aluminum nanoparticles as etch stops, forming rounded spikes, and depositing a conductive layer with an AlOx dielectric, allowing for increased surface area and efficient power delivery at lower manufacturing costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If discrete passive devices are mounted onto the first level interconnect layer or implanted into layers during build-up, then package functionality is achieved, but available space decreases due to shrinking design rules
Solution Approach 1:
The patent merges the capacitor fabrication process with the substrate build-up process, integrating passive device creation into the existing manufacturing flow rather than adding separate discrete device mounting steps. This consolidation maintains package functionality while optimizing space utilization.
Solution Approach 2:
The invention transitions from planar capacitor structures to three-dimensional spiked structures with increased surface area. By creating peaks and valleys in the conductive polymer matrix, the capacitor achieves higher capacitance values within the same footprint, effectively adding a vertical dimension to the design space.
2Adaptability or versatility
If discrete passive devices are used, then package functionality is achieved, but manufacturing cost increases
Solution Approach 1:
The capacitor fabrication is merged with the substrate build-up process, eliminating separate discrete device mounting steps. The spiked capacitor structures are created using standard semiconductor fabrication techniques already present in the manufacturing flow, reducing overall manufacturing complexity and cost.
Solution Approach 2:
The conductive polymer matrix with aluminum nanoparticles serves multiple functions: it provides the capacitor electrode material, acts as an etch stop layer, and forms the spiked structure geometry. This multi-functionality reduces the number of separate materials and processes needed, lowering manufacturing cost.
3Productivity
If design rules are shrunk, then device density increases, but space for passives decreases
Solution Approach 1:
The invention creates three-dimensional spiked structures with peaks and valleys that dramatically increase the effective surface area of the capacitor within the same planar footprint. This vertical dimension allows high device density while preserving sufficient space for passive components.
Solution Approach 2:
The conductive polymer matrix with aluminum nanoparticles creates a porous-like structure with peaks and valleys that increases surface area. This porous architecture enables higher capacitance density without occupying additional planar space, resolving the conflict between device density and passive space.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances passive density, reduces electrical loss, and increases package functionality while maintaining lower production costs, enabling better performance and higher capacitance values.
Implementation Method 1
etching a conductive polymer matrix with aluminum nanoparticles as etch stops, forming rounded spikes
Implementation Method 2
aluminum may then be sputtered across the surface and oxidized to form an AlOx dielectric layer
Implementation Method 3
aluminum may then be sputtered across the surface and oxidized to form an AlOx dielectric layer
Data Source
AI summary
Disclosed herein are microelectronics package architectures utilizing in-situ high surface area capacitor in substrate packages and methods of manufacturing the same. The substrates may include an anode material, a cathode material, and a conductive material. The anode material may have an anode surface that may define a plurality of anode peaks and anode valleys. The cathode material may have a cathode surface that may define a plurality of cathode peaks and cathode valleys complementary to the plurality of anode peaks and anode valleys. The conductive material may be located at the anode peaks.