Spiking Neural Network Accelerator for Cognitive Processing
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Solution Overview
Problem
Existing accelerator systems based on sequentially programmed digital architectures are insufficient for solving complex computational problems related to cognition, such as real-time image recognition, sound localization, and reasoning, as they fail to achieve sufficient speed increase for tasks that human brains can easily handle using spiking neural networks.
Innovation Solution
An accelerator system incorporating a spiking neural network with digital neuron and synapse circuits integrated into an application-specific integrated circuit (ASIC) or programmable logic device, utilizing spike time-dependent plasticity for learning and pattern recognition, and communicating through an Address Event Representation bus, allowing for autonomous learning and complex non-linear function performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If sequentially programmed digital computer architectures are used, then device complexity is reduced and ease of manufacture is improved, but processing speed and efficiency for complex cognitive tasks are insufficient
Solution Approach 1:
The patent replaces traditional sequentially programmed digital computer architectures with a spiking neural network architecture that mimics biological neural processing. This substitution enables parallel processing of complex cognitive tasks through event-driven spike propagation, achieving significantly higher processing speed for tasks like image recognition and sound localization while maintaining manageable device complexity through specialized hardware design.
Solution Approach 2:
The spiking neural network is divided into multiple independent neuron circuits that can process information simultaneously. Each neuron circuit operates autonomously based on received spikes, enabling parallel processing across the network. This segmentation allows the system to achieve high processing speed for complex tasks while keeping individual neuron units relatively simple in structure.
2Productivity
If the number of computing units and clock rate are increased, then processing power is enhanced, but energy consumption and system complexity increase
Solution Approach 1:
The spiking neural network uses event-driven periodic action where neurons only activate and transmit signals when necessary, based on incoming spike patterns. This sparse, periodic activation pattern allows the network to achieve high processing power for cognitive tasks while consuming energy only during actual computation events, rather than continuously clocking all computing units.
Solution Approach 2:
The network achieves high processing power through self-organizing spike propagation patterns that naturally emerge from the interconnected neuron circuits. The system serves itself by automatically routing spikes through appropriate pathways based on learned connections, eliminating the need for centralized control and reducing the energy overhead associated with managing large numbers of computing units.
3Productivity
If spiking neural networks are implemented for complex cognitive tasks, then processing speed for pattern recognition is significantly improved, but device complexity and manufacturing difficulty increase
Solution Approach 1:
The patent implements spiking neural networks by changing the fundamental operating parameters from traditional von Neumann architecture to event-driven spike timing. This parameter change enables high-speed pattern recognition through temporal coding and spike time-dependent plasticity, while the standardized neuron circuit design and modular architecture help manage manufacturing complexity through consistent design rules and fabrication processes.
Data Source
AI summary
A configurable spiking neural network based accelerator system is provided. The accelerator system may be executed on an expansion card which may be a printed circuit board. The system includes one or more application specific integrated circuits comprising at least one spiking neural processing unit and a programmable logic device mounted on the printed circuit board. The spiking neural processing unit includes digital neuron circuits and digital, dynamic synaptic circuits. The programmable logic device is compatible with a local system bus. The spiking neural processing units contain digital circuits comprises a Spiking Neural Network that handles all of the neural processing. The Spiking Neural Network requires no software programming, but can be configured to perform a specific task via the Signal Coupling device and software executing on the host computer. Configuration parameters include the connections between synapses and neurons, neuron types, neurotransmitter types, and neuromodulation sensitivities of specific neurons.