Spiking Neural Network Processor Architecture for Convolution Efficiency
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing hardware implementations of spiking convolutional neural networks are limited by the von Neumann bottleneck, leading to high processing time and power consumption due to their reliance on digital-memory data buses and conventional processing units, which are not optimized for spiking networks and have insufficient synaptic precision, making them unsuitable for rapid data processing applications.
Innovation Solution
A processor architecture optimized for spiking convolutional neural networks that includes convolution modules with elementary processing units capable of matching weight coefficients in parallel, independent of the number of neurons, allowing for efficient computation of convolution layers with minimal memory and processor usage, and supporting high synaptic precision.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If conventional processing units with digital-memory data buses are used to implement spiking convolutional neural networks, then the implementation is compatible with standard hardware architectures, but the processing time and power consumption increase significantly due to the von Neumann bottleneck
Solution Approach 1:
The system segments the convolutional neural network computation into multiple processing units, each handling specific neurons and their associated weight coefficients. This segmentation allows parallel processing of different neuron computations simultaneously, breaking the von Neumann bottleneck by distributing data access across multiple units rather than relying on a single centralized memory-bus interface.
Solution Approach 2:
The patent introduces a specialized intermediary structure where weight coefficients are stored locally in each processing unit rather than in centralized digital memory. This intermediary storage eliminates the need for continuous data transfer between memory and processing units, directly addressing the von Neumann bottleneck by decoupling data access from the main memory-bus interface.
2Ease of manufacture
If conventional processing units are used with standard digital-memory data buses, then the system can be implemented with standard hardware, but the synaptic precision is insufficient for accurate spiking neural network computation
Solution Approach 1:
Each processing unit is equipped with local storage for weight coefficients specific to its assigned neurons, rather than using uniform digital-memory storage across the entire system. This local quality approach allows each unit to maintain high-precision weight coefficients tailored to its computational needs, improving synaptic precision while avoiding the limitations of standardized digital-memory interfaces.
3Productivity
If the number of processing units is increased to handle more neurons in parallel, then the processing speed improves, but the memory and processor requirements increase
Solution Approach 1:
Each processing unit is designed as a universal module capable of handling multiple neurons and their associated computations. The units can be configured to process different sets of neurons depending on the specific convolutional layer requirements, allowing the system to achieve high processing speeds with a manageable number of multi-functional units rather than requiring dedicated units for each neuron.
Solution Approach 2:
The patent merges the storage of weight coefficients and the processing of neuron computations within the same processing unit. This merging eliminates the need for separate memory structures for each neuron, reducing overall system complexity while enabling parallel processing. The combined unit structure allows multiple neurons to be processed simultaneously using shared weight coefficient storage within each unit.
Data Source
AI summary
A processor for computing at least one convolution layer of a convolutional neural network is provided, in response to an input event, the convolutional neural network comprising at least one convolution kernel, the convolution kernel containing weight coefficients. The processor comprises at least one convolution module configured to compute the one or more convolution layers, each convolution module comprising a set of elementary processing units for computing the internal value of the convolution-layer neurons that are triggered by the input event, each convolution module being configured to match the weight coefficients of the kernel with certain at least of the elementary processing units of the module in parallel, the number of elementary processing units being independent of the number of neurons of the convolution layer.