Semiconductor Spin Array for Ising Model Ground State Search

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Solution Overview

Problem

Current methods for searching the ground state of an Ising model, such as using superconductive devices or simulated annealing, face challenges with high costs and scalability issues due to the need for advanced cooling systems and multiple pseudo-random number generators.

Innovation Solution

A semiconductor device configured with a spin array, memory cells for spin values and interaction coefficients, a random number generator, and a bit regulator that supplies random bits to all spin units, allowing for efficient ground state search with reduced hardware complexity and cost.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If superconductive devices are used to search for ground state utilizing quantum fluctuation, then the ability to escape from local solution is improved, but the system requires advanced cooling systems which increases cost and makes large-scale implementation difficult

Engineering Contradiction:
Improveability to escape from local solutionVSAvoidcooling system requirement
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent replaces the mechanical cooling system required by superconductive devices with a semiconductor-based simulated annealing system that operates at standard temperatures. This substitution eliminates the complex cooling infrastructure while maintaining the ability to escape local optima through controlled random bit supply and probabilistic state transitions.

Inventive Principle:
Principle #28Mechanics substitution (Replace mechanical system)

Solution Approach 2:

The patent changes the operating temperature parameter from cryogenic temperatures (superconductive) to standard semiconductor operating temperatures. This parameter change allows the system to function without advanced cooling systems while still implementing quantum-like fluctuation effects through pseudo-random number generation and probabilistic state updates.

Inventive Principle:
Principle #35Parameter changes

2Productivity

If multiple pseudo-random number generators are mounted in every arithmetic unit to achieve parallelism, then the annealing operation speed is improved, but the circuit scale is enlarged and cost is increased

Engineering Contradiction:
Improveannealing operation speedVSAvoidcircuit scale
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The patent merges multiple random number generation functions into a single centralized pseudo-random number generator. This single generator supplies random bits to all spin units through shared communication pathways, eliminating the need for multiple distributed generators while maintaining parallel annealing operations across all spin units.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The single pseudo-random number generator serves all spin units simultaneously, making it a universal component that supports parallel operations across the entire system. This multi-functional approach allows one generator to fulfill the role that would otherwise require multiple dedicated generators, reducing overall circuit complexity.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Data Source

PatentUS9946513B2Semiconductor device and information processing system
Publication Date: 2018.04.17 HITACHI LTD
  • US9946513B2 patent drawing
  • US9946513B2 patent drawing
  • US9946513B2 patent drawing

AI summary

A spin unit provided with a memory cell that stores a value of one spin of an Ising model, a memory cell that stores an interaction coefficient from an adjacent spin which interacts with the corresponding spin, a memory cell that stores an external magnetic field coefficient of the one spin and circuits that determine the next state of the one spin on the basis of a product of a value of each adjacent spin and the corresponding interaction coefficient and the external magnetic field coefficient is configured, the semiconductor device is provided with a spin array where the plural spin units are arranged and connected on a two-dimensional plane on a semiconductor substrate, a random number generator and a bit regulator, the bit regulator operates output of the random number generator and supplies a random bit to all spin units in the spin array via one wire.