Semiconductor Spin Cell Apparatus for Ising Model Optimization

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Solution Overview

Problem

Existing semiconductor integrated circuit apparatuses for Ising models face challenges in efficiently searching for ground states due to the vast number of spin combinations, often resulting in local optimum solutions and high costs associated with large-scale apparatus fabrication, particularly when using quantum fluctuations or pseudorandom number generators for parallelism.

Innovation Solution

A semiconductor integrated circuit apparatus comprising plural spin cells with memory cells, computing circuits, and modification circuits that invert computed results to avoid local optimum solutions, thereby reducing the circuit scale and preventing increased costs.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If quantum fluctuations by superconductive elements are used to escape local solutions, then the ability to find ground states is improved, but the apparatus requires sophisticated cooling systems and becomes expensive and difficult to fabricate

Engineering Contradiction:
Improveability to escape local solutionsVSAvoidapparatus complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent replaces the mechanical/physical system of superconductive elements requiring cooling systems with a semiconductor-based computational system that uses software-controlled random number generation and probabilistic algorithms to achieve the same effect of escaping local solutions, thereby eliminating the need for sophisticated cooling infrastructure

Inventive Principle:
Principle #28Mechanics substitution (Replace mechanical system)

Solution Approach 2:

The patent uses pseudorandom number generators to simulate the statistical behavior of quantum fluctuations, creating a computational model that replicates the effect of quantum effects without requiring actual quantum hardware, thus achieving similar optimization capabilities with standard semiconductor technology

Inventive Principle:
Principle #26Copying

2Productivity

If pseudorandom number generators are mounted on each computing unit for parallelism, then the speed of annealing operations is improved, but the circuit scale increases and fabrication cost rises

Engineering Contradiction:
Improveannealing operation speedVSAvoidcircuit scale
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The patent merges the random number generation function into the existing memory cell structure, where the same memory cell that stores spin values also generates pseudorandom numbers during the annealing process, thereby eliminating the need for separate random number generator circuits and reducing overall circuit scale

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The memory cells are designed to perform multiple functions: storing spin configuration values, generating pseudorandom numbers for probabilistic transitions, and participating in the energy calculation, thereby achieving parallelism without requiring dedicated random number generation hardware for each computing unit

Inventive Principle:
Principle #6Universality (Multi-functionality)

Data Source

PatentUS10073655B2Semiconductor integrated circuit apparatus
Publication Date: 2018.09.11 HITACHI LTD
  • US10073655B2 patent drawing
  • US10073655B2 patent drawing
  • US10073655B2 patent drawing

AI summary

A semiconductor integrated circuit apparatus 23 is used for obtaining an optimum solution using an Ising model, and the semiconductor integrated circuit apparatus 23 includes plural spin cells 1 that are connected with each other. Here, each spin cell 1 includes: a memory cell 9(N) for memorizing a spin value; a computing circuit 10 for computing interactions among the plural spin cells that are connected with each other; a memory circuit 4 for holding at least one-bit data; and an inversion logic circuit LG capable of modifying a computed result obtained by the computing circuit in accordance with data held by the memory circuit 4. The computed result modified by a modification circuit in accordance with the data held by the memory circuit is memorized in the memory cell 9(N) included in each spin cell 1.