Spin FET Logic Circuit Timing to Prevent Through Current
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Solution Overview
Problem
Conventional reconfigurable logic circuits using spin transistors experience high power consumption due to through currents during normal operation, which is inefficient and wasteful.
Innovation Solution
The semiconductor integrated circuit design incorporates an n-channel spin FET with a magnetic tunnel junction or magneto-semiconductor junction that can switch between high and low resistance states, combined with a p-channel FET and a control circuit to manage power supply and input signals, preventing through currents by controlling the timing of transistor operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a conventional reconfigurable logic circuit using a spin transistor is operated in normal mode, then the logic circuit can perform computation and data storage functions, but a large through current is generated between the first and second power supply potentials, causing high power consumption
Solution Approach 1:
The patent applies periodic action by controlling the p-channel FET to turn on and off in timed intervals, allowing current to flow only during specific periods when needed for computation, rather than continuously. This periodic switching of the p-channel FET enables the logic circuit to perform its reconfigurable functions only when necessary, eliminating wasteful through currents during idle periods and significantly reducing overall power consumption while maintaining adaptability
2Reliability
If the n-channel spin FET is used to store data nonvolatilely, then the circuit maintains data without power, but through currents still occur during normal operation mode
Solution Approach 1:
The patent applies preliminary action by pre-charging the output terminal before the n-channel spin FET switches states. This preliminary charging ensures that the output terminal is ready to accept and maintain the data state from the spin FET without requiring continuous current flow. The p-channel FET is turned on in advance to charge the output terminal, then turned off to allow the spin FET to maintain the state nonvolatilely, preventing energy waste while preserving data storage reliability
Solution Approach 2:
The patent introduces an intermediary p-channel FET between the power supply and the n-channel spin FET. This intermediary device controls the flow of current, allowing it to pass only when needed for writing or reading data states. The p-channel FET acts as a gatekeeper that enables the spin FET to store data nonvolatilely without generating through currents during normal operation, thus eliminating energy waste while maintaining reliable nonvolatile storage
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design effectively reduces power consumption by preventing through currents during normal operation, allowing the circuit to reconfigure logic functions without unnecessary energy usage, while maintaining nonvolatile data storage capabilities.
Implementation Method 1
an n-channel spin FET including one of a magnetic tunnel junction and a magneto-semiconductor junction which has one of a high resistance state and a low resistance state
Implementation Method 2
an n-channel spin FET including one of a magnetic tunnel junction and a magneto-semiconductor junction which has one of a high resistance state and a low resistance state
Data Source
AI summary
A semiconductor integrated circuit includes an n-channel spin FET including one of a magnetic tunnel junction and a magneto-semiconductor junction, the n-channel spin FET including a gate terminal to receive an input signal, a source terminal to receive a first power supply potential, and a drain terminal connected to an output terminal, a p-channel FET including a gate terminal to receive a clock signal, a source terminal to receive a second power supply potential, and a drain terminal connected to the output terminal, a subsequent circuit connected to the output terminal, and a control circuit which turns on the p-channel FET to start charging the output terminal, then turns off the p-channel FET to end the charging, and supplies the input signal to the gate terminal of the n-channel spin FET.