Spin Hall Effect Memory Cell for Leakage Reduction
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Solution Overview
Problem
Current memory devices, such as STT-MRAMs and RRAMs, face challenges in reducing cell size for high integration, efficient multiple writing, and accurate read operations due to interference and leakage currents in cross-point devices.
Innovation Solution
The implementation of a memory device using a spin hall effect with a magnetic tunnel junction (MTJ) cell, where a bit line with spin hall coupling materials applies a spin current to the MTJ cell, allowing for reduced cell size, independent operation, and parallel biasing during read operations, minimizing interference and leakage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a transistor is formed in each cell to minimize interference, then cell isolation is improved, but cell size increases to 6 F2 or more
Solution Approach 1:
The invention extracts the transistor from the cell structure, placing it outside the cell in a shared region. This allows the cell itself to be reduced to minimal size while the transistor provides the necessary isolation and control functions for multiple cells sharing common bit lines and word lines.
Solution Approach 2:
The invention implements a shared transistor structure where a single transistor serves multiple cells by controlling access to common bit lines. This multi-functional approach allows one transistor to provide isolation and control for multiple cells, dramatically reducing the total transistor count and enabling smaller cell sizes.
2Productivity
If current flows through each unit cell for writing, then data can be written to multiple cells, but current magnitude must increase three times for three cells
Solution Approach 1:
The invention introduces a shared transistor as an intermediary control element that regulates current flow to multiple cells through common bit lines. This mediator allows selective activation of individual cells during multiple writing operations, enabling parallel writes without requiring proportional increases in current magnitude for each additional cell.
3Area of moving object
If a cross point device is used, then cell size is reduced, but leakage current flows to adjacent cells during read operation
Solution Approach 1:
The invention extracts the leakage current problem by removing the transistor from within the cell and placing it in a shared region. This separation allows the cell to maintain its small cross-point structure while the external transistor provides controlled access, preventing leakage current from flowing to adjacent cells during read operations through proper biasing and control.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables stable, high-speed memory operations with increased integration, independent write and read margins, and efficient multi-writing capabilities, overcoming limitations of series writing and leakage-induced errors.
Implementation Method 1
a bit line including a material layer applying a spin current to the MTJ cell
Data Source
AI summary
A memory device using a spin hall effect, and methods of manufacturing and operating the memory device, include applying a first operational current to a bit line of the memory device such that a spin current is applied to a magnetic tunnel junction (MTJ) cell coupled to the bit line due to a material in the bit line, wherein the bit line is electrically connected to a word line via the MTJ cell, and the word line intersects the bit line.