Embedding Spin Hall MTJ Devices in Logic Processors
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Solution Overview
Problem
Traditional spin torque transfer magnetoresistive random access memory (STT-MRAM) devices face challenges with high voltage and current density during programming, leading to cell size limitations and energy inefficiency due to large write switching current and voltage requirements.
Innovation Solution
The integration of spin hall effect (SHE) MTJ devices into logic processors using a device-first process flow with subtractively etched SHE metal lines, allowing for low-energy and low-latency write operations through the use of giant spin hall effect magnetic tunnel junctions with optimized material stacks and geometries.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If traditional STT-MRAM devices are used for non-volatile embedded memory, then non-volatility and energy efficiency are improved, but high voltage and current density problems occur during programming
Solution Approach 1:
The patent changes the fundamental writing mechanism parameter from spin torque transfer (requiring high current through MTJ) to spin Hall effect (using current through SHE metal layer). This parameter change in the physical mechanism allows achieving the same magnetic switching function with lower voltage and current density, resolving the contradiction between energy efficiency and harmful high voltage/current density effects.
Solution Approach 2:
The patent introduces a spin Hall effect metal layer as an intermediary component between the current path and the MTJ device. The current flows through this intermediary SHE metal layer rather than directly through the MTJ tunnel junction, which mediates the transfer of spin angular momentum to the free layer. This intermediary approach enables low-voltage writing while maintaining non-volatility and energy efficiency.
2Stability of the object's composition
If traditional STT-MRAM devices are used, then non-volatility is achieved, but cell size limitations occur due to large write switching current requirements
Solution Approach 1:
The patent changes the current path parameter from vertical through MTJ to lateral through SHE metal, and modifies the device structure to include SHE metal layer integrated with the MTJ stack. This structural and operational parameter change enables smaller cell size while maintaining non-volatility, as the writing current no longer needs to pass through the high-resistance MTJ tunnel junction.
3Reliability
If conventional MTJ based devices are used, then memory functionality is achieved, but large write current and voltage requirements limit density
Solution Approach 1:
The patent changes multiple parameters simultaneously: the current path (lateral through SHE metal instead of vertical through MTJ), the switching mechanism (spin Hall effect instead of spin torque transfer), and the device structure (integrated SHE metal layer with MTJ stack). These parameter changes enable higher density memory arrays while maintaining reliable memory functionality, as the reduced current and voltage requirements allow for smaller, more densely packed cells.
Solution Approach 2:
The patent employs a composite structure combining spin Hall effect metal layer with magnetic tunnel junction stack, creating a hybrid device that leverages the advantages of both components. The SHE metal provides efficient spin-charge conversion with low power, while the MTJ stack provides non-volatile storage, achieving high density through this composite material approach.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables high-speed writing at lower switching voltage and energy, overcoming the density and efficiency limitations of traditional STT-MRAM by embedding area-efficient 2T-1MTJ SHE STT-MRAM bit cell arrays within logic processors.
Implementation Method 1
giant spin hall effect magnetic tunnel junctions
Data Source
AI summary
Approaches for embedding spin hall MTJ devices into a logic processor, and the resulting structures, are described. In an example, a logic processor includes a logic region including fin-FET transistors disposed in a dielectric layer disposed above a substrate. The logic processor also includes a memory array including a plurality of two-transistor one magnetic tunnel junction (MTJ) spin hall electrode (2T1MTJ SHE) bit cells. The transistors of the 2T1MTJ SHE bit cells are fin-FET transistors disposed in the dielectric layer.