Embedding Spin Hall MTJ Devices in Logic Processors
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Solution Overview
Problem
Traditional spin torque transfer magnetoresistive random access memory (STT-MRAM) devices face challenges with high voltage and current density during programming, leading to cell size limitations and energy inefficiency due to large write switching current and voltage requirements.
Innovation Solution
The integration of damascene-based approaches for embedding spin hall MTJ devices into logic processors, utilizing a 2T-1MTJ spin hall effect STT-MRAM bit cell structure with a giant spin hall effect MTJ device to achieve low-energy and low-latency write operations, where the spin hall metal layer is patterned using a damascene process and connected to underlying metallization via thin vias.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by stationary object
If traditional STT-MRAM devices are used for non-volatile embedded memory, then non-volatility and energy efficiency are improved, but high voltage and current density problems occur during programming
Solution Approach 1:
The patent changes the write mechanism parameter from spin torque transfer (requiring high current through MTJ) to spin hall effect (using current through spin hall metal layer). This parameter change in the physical mechanism allows achieving the same memory write function with lower voltage and current density, resolving the contradiction between energy efficiency and harmful high voltage/current density effects.
Solution Approach 2:
The spin hall metal layer acts as an intermediary element that converts charge current into spin current via the spin hall effect. This intermediary mechanism enables memory programming without requiring high current density through the MTJ device itself, thus maintaining energy efficiency while avoiding high voltage and current density problems.
2Reliability
If traditional STT-MRAM with drive transistor is used, then sufficient spin current is provided for writing, but cell size limitation occurs due to large write current and select transistor requirements
Solution Approach 1:
The spin hall metal layer serves as an intermediary that generates spin current more efficiently. By using the spin hall effect in a dedicated metal layer, sufficient spin current is achieved with lower overall current requirements, allowing smaller transistor sizes and reduced cell area while maintaining reliable write capability.
Solution Approach 2:
Changing the write current path from through-MTJ to through-spin hall metal layer changes the current density distribution. This parameter change allows the same spin current to be achieved with lower peak current density, enabling smaller device dimensions and reduced cell size.
3Reliability
If conventional MTJ based devices are used, then non-volatile memory function is achieved, but large write current (>100 μA) and voltage (>0.7 V) requirements limit density
Solution Approach 1:
The patent changes the write voltage and current parameters by using spin hall effect instead of direct spin torque transfer. This parameter change reduces the write voltage requirement from >0.7V to lower values and reduces write current from >100μA to lower values, enabling higher memory density while maintaining non-volatile memory function.
Solution Approach 2:
The spin hall metal layer acts as an intermediary that decouples the write current path from the MTJ tunnel path. This allows the MTJ to maintain its non-volatile memory function while the spin hall layer handles the current generation, enabling lower current and voltage operation for higher density.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables high-speed writing at lower switching voltage and energy, overcoming the density and efficiency limitations of traditional STT-MRAM by embedding area-efficient 2T-1MTJ SHE STT-MRAM bit cell arrays into logic processors, enhancing performance and capacity without the need for significant redesign.
Implementation Method 1
utilizing a 2T-1MTJ spin hall effect STT-MRAM bit cell structure with a giant spin hall effect MTJ device to achieve low-energy and low-latency write operations
Data Source
AI summary
Damascene-based approaches for embedding spin hall MTJ devices into a logic processor, and the resulting structures, are described. In an example, a logic processor includes a logic region including a metallization layer. The logic processor also includes a memory array including a plurality of two-transistor one magnetic tunnel junction (MTJ) spin hall effect electrode (2T-1MTJ SHE electrode) bit cells. The spin hall effect electrodes of the 2T-1MTJ SHE electrode bit cells are disposed in a lower dielectric layer laterally adjacent to the metallization layer of the logic region. The MTJs of the 2T-1MTJ SHE electrode bit cells are disposed in an upper dielectric layer laterally adjacent to the metallization layer of the logic region.