Giant Spin Hall Retention Latch for Zero Leakage Data Storage
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Solution Overview
Problem
Microprocessors in electronic devices continue to consume power due to leakage currents even in sleep or hibernation mode, which is particularly problematic for mobile devices where battery life is critical, and existing methods to mitigate this issue, such as lowering supply voltage or using volatile shadow latches, lead to complex circuits and long wake-up times.
Innovation Solution
A non-volatile high noise margin (NVHNM) data retention circuit utilizing the Giant Spin Hall effect to convert complementary charge bits of a latch/SRAM into complementary non-volatile spin bits, allowing for zero-leakage data retention by using a coupled giant spin hall latch with spin transfer torque stacks and switches to manage data states during sleep and wake modes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If supply voltage is lowered to Vccmin to reduce leakage power, then power leakage is reduced, but current leakage persists because Vccmin is non-zero (0.4V to 0.5V)
Solution Approach 1:
The patent changes the fundamental operating parameter from voltage-based charge storage to spin-state-based storage. By using magnetoresistive RAM (MRAM) cells with spin-transfer torque (STT) mechanisms, the system achieves data retention without relying on voltage levels, thereby eliminating leakage power while maintaining data integrity during sleep mode
Solution Approach 2:
The patent replaces the electrical charge-based retention mechanism with a magnetic spin-based mechanism. The STT-MRAM technology uses spin-polarized current to switch magnetic moments, substituting the traditional electrical field-based charge storage with a magnetic field-based spin state storage, which does not suffer from leakage currents
2Loss of energy
If volatile shadow latches are used to lower leakage, then power consumption is reduced, but circuit complexity increases significantly
Solution Approach 1:
The patent extracts the data retention function from the volatile logic circuitry by implementing a separate, dedicated non-volatile storage layer using STT-MRAM. This separation allows the volatile latch to be powered down completely while data is safely stored in the non-volatile memory, eliminating the need for complex shadow latch circuits
Solution Approach 2:
The patent introduces an intermediary conversion mechanism that translates volatile data states to non-volatile spin states and vice versa. This intermediary layer using STT-MRAM cells acts as a bridge between the volatile logic and non-volatile storage, simplifying the overall system architecture compared to direct volatile shadow latch implementations
3Loss of energy
If data is transferred to non-volatile RAM during sleep mode, then leakage is reduced, but wake-up time increases due to data transfer requirements
Solution Approach 1:
The patent performs preliminary action by maintaining spin-state data in the STT-MRAM cells during active mode, so that when sleep mode is entered, the data is already in the non-volatile storage medium and requires no additional transfer time during wake-up. The spin states are prepared and stored in advance, enabling instant restoration of data upon power restoration
Solution Approach 2:
The patent makes the STT-MRAM cells serve dual functions: acting as primary storage during active mode and as non-volatile retention storage during sleep mode. This multi-functionality eliminates the need for separate volatile and non-volatile storage regions and the associated data transfer overhead, as the same physical cells handle both roles
4Duration of action of stationary object
If ferroelectric storage is implemented adjacent to volatile storage, then non-volatile retention is achieved, but dynamic power consumption remains substantial
Solution Approach 1:
The patent changes the physical parameter used for data storage from electric dipole moments in ferroelectric materials to magnetic spin moments in ferromagnetic layers. This parameter change from electrical to magnetic domain enables true non-volatile storage with near-zero power consumption during retention, as magnetic states do not require continuous power to maintain
Solution Approach 2:
The patent substitutes the ferroelectric switching mechanism with a magnetoresistive switching mechanism using spin-transfer torque. Instead of using electric fields to switch ferroelectric polarization, the system uses spin-polarized current to switch magnetic moments, replacing the ferroelectric effect with a magnetic effect that consumes negligible power during data retention
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enables seamless and efficient data retention with zero or near-zero leakage, reducing power consumption and shortening wake-up times, making it suitable for microprocessor power gating and other applications.
Implementation Method 1
a giant spin hall metal coupled to the write switch and the read switch and configured to pass the charge current of the external latch
Implementation Method 2
a first spin transfer torque (STT) stack at a first side of the giant spin hall metal; and a second STT stack at a second side of the giant spin hall metal
Data Source
AI summary
A non-volatile data retention circuit, which is configured to store complementary volatile charge states of an external latch, comprises a coupled giant spin hall latch configured to generate and store complementary non-volatile spin states corresponding to the complementary volatile charge states of the external latch in response to receiving a charge current from the external latch, and to generate a differential charge current signal corresponding to the complementary non-volatile spin states in response to application of a read voltage, a write switch coupled to the coupled giant spin hall latch and configured to selectively enable flow of the charge current from the external latch to the coupled giant spin hall latch in response to a sleep signal, and a read switch coupled to the coupled giant spin hall latch and to selectively enable the application of the read voltage to the coupled giant spin hall latch.