Spin-on interlayer dielectric for non-planar transistors

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Solution Overview

Problem

In the fabrication of non-planar transistors, such as tri-gate and FinFETs, the formation of a void-free first level interlayer dielectric material layer that exerts tensile strain on source/drain regions is challenging, affecting transistor performance.

Innovation Solution

A spin-on coating technique followed by oxidation and annealing is used to form a void-free first level interlayer dielectric material layer, which exerts tensile strain on the source/drain regions, enhancing channel mobility and drive currents.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If conventional deposition techniques are used to form the interlayer dielectric layer, then the process is simple and fast, but voids form in high aspect ratio structures and tensile strain is not achieved

Engineering Contradiction:
Improvegap fill qualityVSAvoidprocess complexity
Core Design Contradiction:
Manufacturing precisionVSDevice complexity

Solution Approach 1:

The patent changes the physical and chemical parameters of the dielectric material by using a spin-on-glass (SOG) material that can be oxidized. The oxidation process transforms the SOG into a denser material that exerts tensile strain on the source/drain regions. This parameter change enables both void-free gap fill in high aspect ratio structures and the desired tensile strain effect, resolving the contradiction between manufacturing precision and process complexity.

Inventive Principle:
Principle #35Parameter changes

Solution Approach 2:

The patent utilizes a phase transition approach by oxidizing the spin-on-glass material. The oxidation process converts the as-deposited SOG phase into an oxidized phase with different properties - specifically, the oxidized material is denser and generates tensile strain. This phase transition enables the material to fill high aspect ratio gaps without voids while simultaneously providing the mechanical strain needed for enhanced carrier mobility.

Inventive Principle:
Principle #36Phase transitions

2Productivity

If the interlayer dielectric material is densified to exert tensile strain, then drive current improves, but the deposition and processing becomes more complex

Engineering Contradiction:
Improvedrive currentVSAvoiddeposition ease
Core Design Contradiction:
ProductivityVSEase of manufacture

Solution Approach 1:

The spin-on-glass material is designed to be self-densifying through the oxidation process. Rather than requiring complex external densification equipment or multiple processing steps, the material automatically transforms into a denser state when exposed to oxidation conditions, thereby exerting tensile strain on the source/drain regions. This self-service mechanism improves drive current while avoiding the need for complex additional manufacturing steps.

Inventive Principle:
Principle #25Self-service

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The approach results in improved drive currents of up to 7% for NMOS tri-gate transistors by densifying the interlayer dielectric material and ensuring effective gap fill in high aspect ratio structures.

Implementation Method 1

A spin-on coating technique followed by oxidation and annealing is used to form a void-free first level interlayer dielectric material layer

Methodology Applied
Scientific EffectSpin coating: Spin Coating

Implementation Method 2

A spin-on coating technique followed by oxidation and annealing is used to form a void-free first level interlayer dielectric material layer

Methodology Applied
Scientific EffectOxidation: Oxidation

Implementation Method 3

A spin-on coating technique followed by oxidation and annealing is used to form a void-free first level interlayer dielectric material layer

Methodology Applied
Scientific EffectAnnealing: Annealing

Data Source

PatentUS10998445B2Interlayer dielectric for non-planar transistors
Publication Date: 2021.05.04 TAHOE RES LTD
  • US10998445B2 patent drawing
  • US10998445B2 patent drawing
  • US10998445B2 patent drawing

AI summary

The present description relates the formation of a first level interlayer dielectric material layer within a non-planar transistor, which may be formed by a spin-on coating technique followed by oxidation and annealing. The first level interlayer dielectric material layer may be substantially void free and may exert a tensile strain on the source/drain regions of the non-planar transistor.