Spin-On Metal Oxide Interlayer Dielectric for Void-Free HKMG Gaps
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Solution Overview
Problem
Conventional semiconductor fabrication technologies using silicon oxycarbide (SiOC) for interlayer dielectric (ILD) formation face issues such as voids, increased resistivity due to oxidation, and reduced process window, especially as device sizes shrink below the 5-nanometer technology node.
Innovation Solution
The use of a spin-on metal oxide deposition process to form part of the ILD, which eliminates the need for oxygen-containing gases, ensuring better gap filling and reducing the risk of oxidation, and replaces multiple processing steps with a single fabrication process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If silicon oxycarbide is used to form the interlayer dielectric, then the ILD can be formed with conventional processes, but trapped voids appear in the ILD and resistivity increases due to undesirable oxidation
Solution Approach 1:
The patent changes the material composition parameters by using silicon oxide instead of silicon oxycarbide, and modifies the deposition process parameters by employing spin-on deposition with metal alkoxide precursors rather than conventional CVD processes. This parameter change eliminates the formation of trapped voids and prevents undesirable oxidation while maintaining processability.
Solution Approach 2:
The patent replaces the chemical vapor deposition mechanism with a spin-on deposition mechanism. Instead of using gas-phase chemical reactions that lead to void formation and oxidation, the invention uses liquid precursor deposition followed by thermal processing, which provides better conformal coverage and eliminates the harmful effects of oxygen exposure during deposition.
2Productivity
If device geometry size is decreased to increase functional density, then more circuits can be integrated per chip area, but manufacturing precision requirements increase
Solution Approach 1:
The patent achieves local quality improvement by ensuring uniform deposition of the spin-on metal oxide layer across varying topographies. The spin-on process provides conformal coverage in high-aspect-ratio structures and narrow gaps, delivering consistent film thickness and composition at sub-5nm dimensions where precision is critical for maintaining manufacturing yield.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach prevents voids and oxidation, enhances etching selectivity, and reduces fabrication costs and complexity, providing improved semiconductor device performance and reliability.
Implementation Method 1
a spin-on metal oxide deposition process
Implementation Method 2
eliminates the need for oxygen-containing gases, ensuring better gap filling and reducing the risk of oxidation
Data Source
AI summary
A plurality of high-k metal gate (HKMG) structures is formed over a substrate. The (HKMG) structures are separated by a plurality of gaps. The HKMG structures each include a first dielectric layer at an upper surface of the HKMG structure. The gaps are filled with a first conductive material. A portion of the first conductive material is removed in each of the gaps through an etching-back process. A metal oxide layer is formed using a spin-on deposition process. The metal oxide layer is formed over the (HKMG) structures and over the first conductive material. A second dielectric layer is formed over the metal oxide layer. An opening is etched in the second dielectric layer. The opening is etched through the second dielectric layer and through the metal oxide layer. The opening is filled with a second conductive material.