Spine Router Technique for IC Interconnect Routing
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Solution Overview
Problem
Traditional automatic routers for integrated circuits often produce suboptimal interconnect routing with many jogs and bends, leading to inefficient signal propagation, increased resistance, and capacitance, and manual rerouting is time-consuming and prone to design rule violations.
Innovation Solution
A spine router technique that lays down a single spine interconnect in long, thin areas and stitches pins to it, minimizing overall connection distance and signal delay, while avoiding obstacles and optimizing routing quality.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Extent of automation
If traditional automatic routers are used for interconnect routing, then routing automation is achieved, but routing quality deteriorates with many jogs and bends
Solution Approach 1:
The routing process is segmented into two distinct phases: coarse routing that establishes the general path and fine routing that optimizes the actual interconnect geometry. This segmentation allows the system to achieve both automation and high routing quality by addressing different aspects of routing in separate optimized steps.
Solution Approach 2:
The coarse router performs preliminary action by establishing the general routing path before the fine router optimizes the actual interconnect segments. This preliminary structuring enables the fine router to focus on minimizing jogs and bends without having to determine the overall route, thereby improving routing quality while maintaining automation.
2Productivity
If traditional routers produce interconnect routes, then routing is completed, but signal propagation characteristics worsen due to increased resistance and capacitance
Solution Approach 1:
The fine router changes geometric parameters of the interconnect routes by minimizing the number of jogs and bends in the routing paths. This parameter optimization directly improves signal propagation characteristics by reducing resistance and capacitance, thereby enhancing reliability while maintaining routing productivity.
3Manufacturing precision
If manual rerouting is performed to increase linear interconnects, then routing quality improves, but time consumption increases
Solution Approach 1:
The fine router performs self-service by automatically optimizing interconnect routes to minimize jogs and bends without requiring manual intervention. This automated optimization achieves routing quality comparable to or better than manual rerouting while eliminating the time loss associated with manual processes.
4Adaptability or versatility
If more interconnect segments are used to connect pins, then routing flexibility increases, but signal propagation time increases
Solution Approach 1:
The fine router minimizes angular deviations and jogs in interconnect paths, creating smoother, more linear routes. This reduction in path curvature and angular changes decreases the number of effective segments, thereby reducing signal propagation time while maintaining the routing flexibility needed to navigate around obstacles and satisfy design constraints.
Data Source
AI summary
A method and technique of routing interconnects of an integrated circuit providing improved routing quality. In an embodiment of the invention, the technique provides linear spine interconnect routing. In memory array blocks, such as in DRAM and SRAM memory designs, connected pins are generally separated by large distances in a first direction and small distances in a second direction, or a spine or channel region. A route area is defined within the spine region. In one embodiment, obstacles in the route area are identified and corresponding forbidden areas are demarcated. The linear spine interconnect is routed in the first direction within the route area while avoiding the forbidden areas. Pins are connected to the spine interconnect by stitching interconnects. Stitching interconnects are generally routed in the second direction.