Spiral Double-Surround Capacitor Layout for Higher On-Chip Capacitance
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Solution Overview
Problem
Integrated chips face challenges in maximizing capacitance within a limited layout area due to the conventional design of capacitors, which restricts their functional capabilities in analog and digital circuitry.
Innovation Solution
The implementation of a double surround capacitor structure with spiral or polygonal patterns for the electrodes, where the first and second electrodes are not directly connected but surround each other, increasing the effective area and capacitance value without increasing the layout area, by using a dielectric material between them.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If conventional capacitor design is used, then layout area is kept simple, but capacitance value is limited and cannot be maximized
Solution Approach 1:
The patent implements a double surround capacitor structure where a first electrode and a second electrode are nested within each other in a planar configuration. The first electrode extends from a first end to a second end, while the second electrode extends from a second end to a third end, with both electrodes surrounded by a common electrode. This nested arrangement maximizes the effective overlapping area between electrodes, thereby increasing capacitance value without requiring additional layout area.
Solution Approach 2:
The patent transitions from traditional three-dimensional vertical capacitor structures to a planar two-dimensional configuration. By arranging electrodes in a flat, nested pattern on the same plane rather than stacking them vertically, the design achieves higher capacitance density within the constrained layout area, effectively utilizing the planar dimension to maximize electrode overlap.
2Quantity of substance
If electrode area is increased to boost capacitance, then capacitance value improves, but layout area consumption increases
Solution Approach 1:
The nested electrode configuration allows multiple electrodes to occupy the same spatial footprint by arranging them concentrically or in overlapping patterns. The first electrode, second electrode, and common electrode are positioned such that they nest within each other's boundaries, effectively multiplying the functional electrode area without proportionally increasing the physical layout area.
Solution Approach 2:
The patent employs spiral or polygonal patterns for the electrode layouts instead of simple linear or rectangular configurations. These curved and geometric patterns allow the electrodes to pack more efficiently within the available area, increasing the effective overlapping length and area between electrodes while maintaining compact boundaries.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design enhances capacitance values within the same layout area, enabling improved performance in integrated circuits by optimizing space utilization and capacitance, thus supporting more complex circuit functionalities.
Implementation Method 1
a first capacitor and a second capacitor, each including the first electrode, the second electrode, and the dielectric material between the first electrode and the second electrode
Implementation Method 2
a dielectric material between them
Data Source
AI summary
A method includes forming a dielectric layer on a substrate; forming a first spiral electrode, a second spiral electrode, and a spiral common electrode in the dielectric layer, the first spiral electrode extending in a first spiral path, the second spiral electrode extending in a second spiral path, and the spiral common electrode extending in a third spiral path laterally between the first and second spiral paths.