Spiral Gate Line Layout for Fast-Switching Power Converters
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Solution Overview
Problem
Existing semiconductor switching element configurations in power converters experience gate oscillation due to non-uniform switching characteristics and increased parasitic inductance, leading to potential element deterioration and noise issues, with previous solutions reducing switching speed to mitigate oscillation at the cost of increased power loss.
Innovation Solution
The configuration includes a spiral-shaped gate line made of a different material than the gate electrode, arranged in a region separate from the active region, which forms a buried gate inductance component to alleviate the tradeoff between switching speed and high-frequency oscillation reduction, allowing for effective suppression of gate oscillation without increasing power loss.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-generated harmful factors
If a large gate resistance is applied to suppress gate oscillation, then gate oscillation is reduced, but switching speed decreases causing increased power loss
Solution Approach 1:
The gate line is segmented into multiple sections with different resistance values. The gate line includes a first section connected to the gate electrode and a second section connected to the gate pad, where the first section has a smaller resistance value than the second section. This segmentation allows the gate electrode to receive sufficient current for fast switching while the gate pad area maintains higher resistance to suppress oscillation.
Solution Approach 2:
Different sections of the gate line are assigned different resistance characteristics based on their functional requirements. The first section near the gate electrode uses low resistance to enable fast switching, while the second section near the gate pad uses high resistance to suppress gate oscillation. This local differentiation resolves the contradiction by applying appropriate resistance properties to specific locations.
2Power
If multiple semiconductor switching elements are connected in parallel to handle large current, then current capacity increases, but parasitic inductance between elements increases causing non-uniform switching characteristics
Solution Approach 1:
The gate line resistance distribution is made asymmetric with respect to the parallel-connected semiconductor elements. Elements closer to the gate pad experience higher effective resistance which suppresses oscillation, while elements closer to the gate electrode experience lower resistance for fast switching. This asymmetric design allows parallel elements to operate uniformly despite different parasitic inductances.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration reduces gate oscillation while maintaining switching speed, ensuring uniform switching operations and minimizing power loss in parallel-connected semiconductor devices.
Implementation Method 1
The first gate line is formed into a spiral shape. The first gate line is made of a different type of material from the first gate electrode.
Implementation Method 2
gate oscillation becomes a cause for deterioration or breakdown of the semiconductor switching element, and additionally, may become a cause for radiation noise directed toward the outside of the module or conduction noise directed toward an external circuit, for example. The gate oscillation becomes a cause for deterioration or breakdown of the semiconductor switching element, and additionally, may become a cause for radiation noise directed toward the outside of the module or conduction noise directed toward an external circuit, for example.
Data Source
AI summary
To provide a technique of reducing gate oscillation while suppressing reduction in switching speed. A semiconductor device according to the technique disclosed in the present description includes: a first gate electrode in an active region; a gate pad in a first region different from the active region in a plan view; and a first gate line electrically connecting the first gate electrode and the gate pad to each other. The first gate line is formed into a spiral shape. The first gate line is made of a different type of material from the first gate electrode.