Spiral Inductor Capacitive Element Layout for Semiconductor Devices
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The integration of radio circuits into semiconductor devices for wearable devices leads to increased packaging area and potential degradation of inductor characteristics due to capacitive elements being placed in areas with high magnetic flux concentration.
Innovation Solution
A semiconductor device design where the capacitive elements are positioned in the peripheral areas relative to the spiral inductor, either in an upper or lower layer, avoiding the central area with concentrated magnetic flux, thus preventing inductance drop and Q-value reduction while reducing the overall size of the device.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If the capacitive element is disposed in the central area of the spiral inductor to reduce layout area, then the circuit size is reduced, but the inductor characteristics degrade due to magnetic flux concentration
Solution Approach 1:
The patent applies local quality by differentiating the treatment of different regions within the inductor structure. The central area (where magnetic flux is concentrated) is excluded from capacitive element placement, while the peripheral area is designated for capacitive elements. This spatial differentiation of functional zones resolves the contradiction by allowing capacitive elements to occupy only the regions where they do not interfere with magnetic flux, thus maintaining inductor characteristics while achieving compact layout.
2Reliability
If the capacitive element is disposed in the peripheral area of the spiral inductor, then the inductor characteristics are maintained, but the layout area increases
Solution Approach 1:
The patent utilizes another dimension (vertical layering) to resolve the area conflict. By forming the capacitive element in an upper-layer or lower-layer position corresponding to the peripheral area, the design transitions from a two-dimensional planar arrangement to a three-dimensional stacked configuration. This dimensional change allows the capacitive element to be positioned in the peripheral region without increasing the footprint area, as it occupies vertical space above or below the inductor plane, thereby maintaining compact layout while preserving inductor performance.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration effectively suppresses the degradation of inductor characteristics and reduces the size of the semiconductor device by blocking the path of eddy currents and preventing inductance drops, while also minimizing the layout area.
Implementation Method 1
This configuration effectively suppresses the degradation of inductor characteristics and reduces the size of the semiconductor device by blocking the path of eddy currents and preventing inductance drops
Data Source
AI summary
A semiconductor device capable of reducing in size thereof and suppressing degradation in the characteristics of circuit components is provided. The semiconductor device includes an LC circuit comprised of a spiral inductor provided over a semiconductor substrate and a capacitive element coupled with the spiral inductor. The spiral inductor includes a central area encircled with a metal wiring and a peripheral area other than the central area. The capacitive element is formed in an upper-layer or a lower-layer position corresponding to the peripheral area other than the central area.