Embedded Spiral Inductor Impedance Control
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The reduction in overall package form factors of multi-layered semiconductor packages leads to low inductances and impedance mismatches, causing undesirable signaling issues, especially in high-speed systems due to high capacitance of solder balls and IC dies.
Innovation Solution
Incorporating a spiral inductor or trace within the semiconductor package to provide a desired impedance by compensating for capacitance, with the spiral's design parameters such as material, shape, and layout optimized to achieve specific inductance values, thereby maintaining a controlled impedance across the signal path.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If the package form factor is reduced to meet smaller package demands, then the package size decreases, but the inductance in the signal path decreases leading to low impedance and impedance mismatches
Solution Approach 1:
The spiral inductor is embedded within the multi-layer substrate structure, nesting the inductive element inside the package layers rather than placing it externally. This allows the inductor to be integrated into the signal path without increasing the overall package footprint, thus maintaining small form factor while providing the necessary inductance for impedance matching
Solution Approach 2:
The solution transitions from planar trace inductors to three-dimensional spiral inductors that utilize vertical layering within the multi-layer substrate. By winding the conductor in a spiral pattern across multiple layers, the inductance is increased without proportionally increasing the planar area, effectively decoupling inductance from package footprint
2Area of stationary object
If the package footprint is decreased, then the overall package size reduces, but the capacitance of interconnect elements increases causing low impedance
Solution Approach 1:
The patent modifies the electrical parameters of the interconnect by introducing a spiral inductor with specific inductance values (e.g., 0.1nH to 10nH) that compensate for the capacitive effects. By adjusting the spiral geometry (number of turns, trace width, spacing), the inductance parameter is tuned to achieve the desired impedance characteristic despite the reduced footprint increasing capacitance
3Reliability
If spiral inductor is added to adjust impedance, then the impedance matching improves, but the device complexity increases
Solution Approach 1:
The spiral inductor is merged with the existing substrate and interconnect structure, sharing the same fabrication process and material layers. The inductor traces are formed using the same copper deposition and patterning steps as the signal traces, eliminating the need for separate inductor components and reducing overall device complexity
Solution Approach 2:
The multi-layer substrate serves multiple functions: it provides mechanical support, electrical interconnection, and houses the spiral inductor for impedance control. The same substrate layers that carry signal traces also provide the magnetic path and structural framework for the embedded inductor, making the substrate a multi-functional element
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The spiral inductor effectively adjusts the package's impedance, reducing mismatches with IC dies and PCBs, ensuring reliable signaling even at high speeds by tuning inductance to match desired impedance values.
Implementation Method 1
spiral inductor or trace within the semiconductor package to provide a desired impedance by compensating for capacitance
Data Source
AI summary
In some embodiments, the semiconductor package includes a substrate having multiple layers, from a first layer to a final layer, a die coupled to the first layer, an electrical connector such as a solder ball coupled to the final layer, and a spiral trace disposed and electrically coupled between the die and the electrical connector. Inductance of the spiral trace is selected such that the package has a predetermined impedance. Material, cross-sectional area, number and density of windings, and total overall length of the spiral trace are selected accordingly. In other embodiments, the semiconductor package includes a substrate with multiple layers; a die coupled to the first of the layers; an electrical connector coupled to the final layer; and a spiral trace, in or on the substrate. The spiral trace is near the die, and electrically coupled between the die and the electrical connector.