Spiral Radiator Chip Antenna Etching

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Solution Overview

Problem

The existing manufacturing methods for chip antennas result in a larger carrier board volume due to the smaller size of the chip antenna, making them unsuitable for small-sized mobile electronic devices.

Innovation Solution

A method involving dry or wet etching technologies to form a spiral radiator on chip signal elements, with through holes and conductive layers, and subsequent copper-plating processes to reduce the size of both the chip signal elements and their carrier boards, allowing for smaller form factors.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Volume of moving object

If the chip antenna size is reduced, then the antenna is suitable for small-sized mobile electronic devices, but the carrier board volume becomes several times larger than the chip antenna, resulting in poor matching characteristics

Engineering Contradiction:
Improvechip antenna sizeVSAvoidcarrier board volume
Core Design Contradiction:
Volume of moving objectVSVolume of stationary object

Solution Approach 1:

The patent merges the chip antenna and carrier board into a single integrated structure where the radiator is directly formed on the carrier board substrate. This integration eliminates the need for a separate carrier board, allowing both the antenna and its support structure to be scaled down together to match small-sized mobile electronic devices.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The carrier board substrate serves multiple functions: it acts as both the support structure and the radiator for the antenna. By making the substrate itself radiating through etched patterns, the design achieves both mechanical support and electromagnetic radiation functions in a single component, improving size matching.

Inventive Principle:
Principle #6Universality (Multi-functionality)

2Length of moving object

If printing technology, lithography process technology, or wet etching technology is used to manufacture the radiator, then the chip antenna size is reduced, but the carrier board volume remains large to maintain matching characteristics

Engineering Contradiction:
Improvechip antenna dimensionsVSAvoidcarrier board volume
Core Design Contradiction:
Length of moving objectVSVolume of stationary object

Solution Approach 1:

The patent combines the radiator formation process with the carrier board manufacturing process. By etching the radiator pattern directly into the carrier board substrate using wet etching or dry etching, the design achieves miniaturization of both the antenna and carrier board simultaneously, eliminating the mismatch problem.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The patent changes the manufacturing parameters by using etching technologies (wet or dry) instead of printing or lithography, and by directly forming the radiator on the substrate. This allows precise control of the radiator geometry and enables both the antenna and carrier board to be scaled to appropriate sizes for mobile devices.

Inventive Principle:
Principle #35Parameter changes

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

Enables the reduction of both the chip signal element and carrier board sizes, making them suitable for small-sized mobile devices while maintaining effective signal transmission and reception capabilities.

Implementation Method 1

a first pattern layer is formed on the upper metal layer and forming a second pattern layer on the lower metal layer by a wet etching or a dry etching

Methodology Applied
Scientific EffectEtching:

Implementation Method 2

a first cooper-plating process is performed on hole walls of the through holes to form a plurality of first conductive layers

Methodology Applied
Scientific EffectElectroplating: Electroplating

Data Source

PatentUS10595411B2Method for manufacturing chip signal elements
Publication Date: 2020.03.17 POWER WAVE ELECTRONICS
  • US10595411B2 patent drawing
  • US10595411B2 patent drawing
  • US10595411B2 patent drawing

AI summary

A method for manufacturing chip signal elements includes steps as follows. A substrate is provided. A plurality of through holes is drilled, and a plurality of side holes is formed along the through holes. A first cooper-plating process is performed to form a plurality of conductive layers electrically connected to the upper and the lower metal layer. A second cooper-plating process is performed to increase thickness of the conductive layers. A first and a second pattern layers are formed on the substrate by an etching. The first pattern layer is electrically connected to the second pattern layer to form a spiral radiator. An ink is printed on the substrate to cover the spiral radiator and form a solder mask layer. An organic metal process and a plating process are performed to form terminal electrodes. Finally, a single chip signal element having a spiral radiator is formed.