Spiral TSV Interconnect Layout for Flexible 3D Memory Stacking
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Solution Overview
Problem
Current 3D memory devices face challenges in achieving high data reliability, fast memory access, low power consumption, and reduced chip size due to limitations in interconnect design and signal transmission efficiency.
Innovation Solution
The proposed solution involves a semiconductor device architecture with stacked core chips and an interface chip connected via spiral through-substrate vias (TSVs) and microbumps, allowing for efficient signal transmission and power sharing between layers, enabling face-up and face-down chip configurations to optimize wiring and reduce the need for redundant circuits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If traditional vertical TSV interconnects are used in 3D memory devices, then signal transmission speed and power efficiency are improved, but chip design flexibility and wiring optimization are limited
Solution Approach 1:
The patent applies spiral TSV interconnects instead of traditional straight vertical TSVs. The spiral configuration allows signal paths to curve and extend horizontally within the substrate, enabling connections between chips stacked in different orientations (face-up, face-down, or mixed) while maintaining efficient signal transmission. This curved path geometry provides the adaptability needed for flexible chip stacking arrangements.
2Loss of energy
If chips are stacked vertically with standard TSV connections, then interconnect length is reduced and power consumption decreases, but wiring complexity and redundant circuits increase
Solution Approach 1:
The spiral TSV interconnect structure serves multiple functions simultaneously: it provides electrical connection between chips, enables flexible chip orientation arrangements, and reduces the need for additional wiring layers or redundant interconnect structures. This multi-functional design simplifies the overall wiring complexity while maintaining low power consumption benefits of vertical stacking.
3Ease of manufacture
If face-up chip configuration is used, then wiring optimization is improved, but manufacturing complexity and alignment precision requirements increase
Solution Approach 1:
The patent segments the chip stacking configuration into different orientation groups (face-up, face-down, or mixed orientations) that can be independently designed and manufactured. The spiral TSV interconnects provide robust alignment tolerance that allows each chip layer to be manufactured and assembled with standard precision requirements, while the overall stacked configuration achieves wiring optimization through selective orientation arrangement.
Data Source
AI summary
According to one or more embodiments of the disclosure, an apparatus comprises a plurality of core chips that includes a plurality of spiral through-substrate vias (TSVs). The core chips are stacked with one another in a face-to-face manner to define a common channel in first and second core chips, which face each other, of the plurality of core chips. The first core chip and the second core chips include a first function circuit and a second function circuit coupled to the first function circuit, respectively. The first function circuit and the second function circuit provide a logic circuit and a power supply circuit, respectively. The logic circuit receives power from the power supply circuit.