Spiral TSV Interconnect Layout for Faster 3D Memory Access
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Solution Overview
Problem
Current 3D memory devices face challenges in achieving high data reliability, high-speed memory access, low power consumption, and reduced chip size due to limitations in interconnect design and signal transmission efficiency.
Innovation Solution
The proposed solution involves a semiconductor device architecture with a layered structure of core chips stacked on an interface chip, connected via spiral through-substrate vias (TSVs) and microbumps, allowing for efficient signal transmission and power sharing between layers, which reduces chip size and enhances data access speed while minimizing power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If conventional vertical TSV interconnects are used in 3D memory devices, then chip stacking is achieved, but signal transmission distance and power consumption increase
Solution Approach 1:
The patent applies spiral TSVs instead of conventional straight vertical TSVs. The spiral curvature allows the interconnect to remain within a localized region while providing sufficient signal transmission path, reducing both transmission distance and associated power consumption while maintaining memory access speed
2Productivity
If more TSVs are added to increase bandwidth, then data transmission capacity improves, but chip area and manufacturing complexity increase
Solution Approach 1:
The patent transitions from conventional straight vertical TSVs to spiral TSVs, adding a rotational dimension to the interconnect structure. This allows multiple signal paths to be packed into the same vertical footprint, increasing bandwidth without proportionally increasing chip area
3Volume of moving object
If spiral TSVs are implemented for flexible routing, then chip size is reduced, but manufacturing precision requirements increase
Solution Approach 1:
The patent incorporates alignment marks and positioning structures during the TSV formation process. These preliminary positioning features guide the spiral TSV routing and ensure precise alignment between stacked chips, reducing the actual manufacturing precision requirements despite the complex spiral geometry
Data Source
AI summary
According to one or more embodiments of the disclosure, an apparatus comprises a plurality of core chips that includes a plurality of spiral through-substrate vias (TSVs). The core chips are stacked with one another in a face-to-face manner to define a common channel in first and second core chips, which face each other, of the plurality of core chips. The first core chip and the second core chips include a first function circuit and a second function circuit coupled to the first function circuit, respectively. The first function circuit and the second function circuit provide a first clock divider circuit and a second clock divider circuit, respectively. The first and second clock divider circuits are activated to jointly provide a clock division function.