Spiral TSV Memory Stack Layout for Faster 3D Signal Exchange
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Solution Overview
Problem
Current 3D memory devices face challenges in achieving high data reliability, high-speed memory access, low power consumption, and reduced chip size due to limitations in interconnect design and signal transmission efficiency.
Innovation Solution
The implementation of a semiconductor device architecture that stacks core chips on an interface chip using spiral through-substrate vias (TSVs) and microbumps, allowing for efficient signal transmission and power sharing between layers, while alternating the orientation of core chips between face-up and face-down configurations to enhance signal exchange and reduce the need for redundant circuits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If conventional vertical stacking with straight TSVs is used, then chip size reduction is achieved, but signal transmission efficiency and power distribution are limited
Solution Approach 1:
The patent employs spiral-shaped TSVs instead of straight vertical vias. The spiral configuration allows signal paths to extend horizontally across multiple chip layers while maintaining vertical stacking geometry, thereby increasing effective signal transmission distance and enabling more efficient inter-layer communication without increasing overall chip footprint.
Solution Approach 2:
The spiral TSV design transitions from one-dimensional vertical connections to two-dimensional spiral paths within the vertical stacking architecture. This dimensional transformation enables signals to traverse multiple chip layers more efficiently by utilizing both vertical and horizontal space, improving signal transmission speed while maintaining compact chip size.
2Productivity
If more TSVs are added between layers, then bandwidth increases, but manufacturing complexity and cost increase
Solution Approach 1:
The spiral TSV structure serves multiple functions simultaneously: it provides signal transmission paths, power distribution channels, and ground references within a single interconnect element. This multi-functionality increases effective bandwidth without requiring proportionally more separate TSV structures, thereby reducing manufacturing complexity compared to conventional designs that would need separate dedicated signal and power vias.
Solution Approach 2:
The patent combines signal transmission and power distribution functions into the same spiral TSV structure. By merging these functions, the design achieves high bandwidth through efficient signal paths while reducing the total number of separate interconnect structures needed, thus lowering manufacturing complexity and cost.
3Area of stationary object
If core chips are stacked vertically, then chip footprint is reduced, but heat dissipation and power distribution become more difficult
Solution Approach 1:
The spiral TSV configuration extends power distribution paths horizontally within the vertical stacking architecture, allowing power to be distributed more efficiently across multiple chip layers. The curved spiral path increases the effective length of power delivery routes without increasing chip footprint, enabling better power management in the compact 3D structure.
Data Source
AI summary
According to one or more embodiments of the disclosure, an apparatus comprises a plurality of core chips that includes a plurality of spiral through-substrate vias (TSVs). The core chips are stacked with one another in a face-to-face manner to define a common channel in first and second core chips, which face each other, of the plurality of core chips. The first core chip and the second core chips include a first function circuit and a second function circuit coupled to the first function circuit, respectively. The first function circuit and the second function circuit provide the same functions.