Spline-Based Metal Interconnect Routing for Parasitic Reduction
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Solution Overview
Problem
The increasing cumulative resistance and capacitance of semiconductor device interconnects due to shrinking transistor and interconnect sizes adversely impact performance, and existing grid-based modeling and optimization methods become complex and inefficient as the number of grid points increases.
Innovation Solution
Optimizing interconnect routing using spline-based representations that allow curved paths between points, reducing the number of parameters required for modeling and enabling faster optimization of parasitic effects, with fewer computational resources.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If grid-based routing with voxels or mesh points is used to model interconnects, then general applicability and realistic representation are improved, but device complexity and computational resources required increase significantly
Solution Approach 1:
The patent applies curvature by representing interconnect paths as smooth spline curves instead of straight-line grid segments. This allows the routing to follow curved trajectories that better represent physical wire layouts while reducing the number of discrete grid points needed to define the path, thereby maintaining generality without proportionally increasing complexity
Solution Approach 2:
The patent changes the parameter representation from thousands of grid point coordinates to a small number of spline control points and weights. This parameter transformation maintains the ability to represent complex realistic interconnect geometries while dramatically reducing the computational complexity of modeling and optimization
2Ease of manufacture
If grid-based routing constrains interconnects to straight-line paths between grid points, then ease of manufacture is improved, but parasitic effects (resistance and capacitance) worsen due to suboptimal routing paths
Solution Approach 1:
The patent uses curved spline paths to optimize interconnect routing, allowing wires to follow smoother trajectories that can reduce sharp corners and unnecessary length. This curvature-based approach enables better parasitic optimization while still being manufacturable through standard lithography processes that can handle curved patterns
3Measurement precision
If the number of voxels or mesh points in the grid is increased to improve modeling precision, then measurement precision of parasitic characteristics is improved, but device complexity and computational resources required increase
Solution Approach 1:
The patent transforms the parameter representation from a dense grid of thousands of voxel values to a compact representation using spline control points and associated weights. This parameter compression maintains the ability to accurately model parasitic characteristics while dramatically reducing the number of parameters that need to be stored and processed
4Object-generated harmful factors
If spline-based routing with curved paths is used, then parasitic effects are reduced and optimization speed is improved, but ease of manufacture may be impacted due to curved lithography requirements
Solution Approach 1:
The patent employs curved spline paths to reduce parasitic effects by optimizing wire routing geometry. The curved paths can reduce sharp corners, minimize wire length, and improve spacing between adjacent interconnects, all of which reduce resistance and capacitance while remaining compatible with modern lithography capabilities
Data Source
AI summary
The technology involves optimization of spline-based routing of interconnects. According to one aspect, a method includes receiving a set of weights associated with constraints of a circuit to be fabricated. A first routing of interconnects of the circuit is determined that includes a spline corresponding to one of the interconnects having a straight-line profile. Parameters of the spline are adjusted, based on the set of weights, to transition the spline from a straight-line profile to a curved profile. Adjusting the parameters yields a second routing of the interconnects. A value of a merit function of the second routing of the interconnects is determined. A circuit layout of the interconnects for the circuit is generated based on the value of the merit function.