Split Access L2 Cache Reduces Latency
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Solution Overview
Problem
Conventional L2 cache implementations face latency penalties when increasing cache size, as larger caches require all inputs, including addresses, to be available before operations can start, leading to inefficiencies in data access.
Innovation Solution
The proposed memory array configuration allows read access to be split into two cycles, utilizing the set address early to initiate data retrieval in the first cycle, and determining the way address in the second cycle, thereby reducing latency and enabling larger instance sizes without impacting performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If L2 cache size is increased to improve cache hit rate, then cache capacity increases, but access latency increases by 2-3 cycles
Solution Approach 1:
The patent segments the cache access operation into two independent phases: tag access (using set index) and data access (using way address). This segmentation allows the set index to be provided early to initiate tag access, while the way address can be determined later, enabling larger cache sizes without proportionally increasing access latency.
Solution Approach 2:
The patent performs preliminary action by accepting and processing the set index address early, before the full cache address is available. This allows the tag array to be accessed in advance, and the data array access to be initiated earlier, reducing the overall access latency for larger caches.
2Measurement precision
If conventional cache access requires all inputs including way address to be available before operation starts, then address decoding accuracy is ensured, but access latency increases
Solution Approach 1:
The patent segments the address into two parts: set index (provided early) and way address (determined later). This segmentation allows the cache access to begin with the set index without waiting for the complete address, maintaining decoding accuracy through separate tag comparison while reducing latency.
Solution Approach 2:
The patent performs preliminary address decoding using only the set index portion before the complete address is available. The tag array is accessed early with the set index, and the way address is determined subsequently through tag comparison, ensuring accuracy while reducing overall access time.
3Quantity of substance
If larger cache instances are implemented, then cache capacity increases, but timing performance deteriorates
Solution Approach 1:
The patent segments the cache access into independent set index processing and way address determination phases. This allows larger cache instances to be implemented by increasing the tag array size without proportionally increasing the critical path, as the set index processing can begin independently and in parallel with way address determination.
Solution Approach 2:
The patent performs preliminary processing of the set index to initiate tag access before the way address is available. This preliminary action allows larger cache instances to maintain timing performance by overlapping the tag access phase with the way address determination phase, preventing the critical path from scaling linearly with cache size.
Data Source
AI summary
A memory with data array (e.g., L2 cache) addressable in rows and columns and techniques to access data therein are proposed. Unlike conventional data arrays, the proposed memory allows data access to be initiated based on a row (or set) address even though the column (or way) address is not yet available. When the column address is determined, it can be used to select the correct data. Since the data access is started prior to determining the column address, memory access latency is reduced.