Split-Bit Digital Readout Calibration for Counter-Residual Alignment
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Solution Overview
Problem
Split bit digital readouts in advanced focal plane arrays face misalignment issues between the least significant counter bit and the most significant residual bit, leading to unusable output data, particularly in high-performance longwave infrared imaging systems that require large well depths for improved signal-to-noise ratio.
Innovation Solution
A calibration system using a field programmable gate array (FPGA) and digital signal processing (DSP) to align the least significant bits from an analog-to-digital converter with the most significant bits from an in-pixel counter, involving a calibration mode to determine gain and offset values, and applying these corrections to generate aligned digital readouts.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If split bit digital readout is used to increase well depth and reduce ADC power, then signal-to-noise ratio is improved and ADC power is reduced, but misalignment between least significant counter bit and most significant residual bit occurs causing output data to become unusable
Solution Approach 1:
The patent applies preliminary action by performing calibration measurements before normal operation to determine the actual weights of LSB and MSB. The system collects calibration frames with known charge values, calculates the relationship between LSB and MSB weights, and stores calibration data (gain and offset) for later use. This preliminary characterization of the split-bit relationship enables accurate correction during subsequent imaging operations, resolving the misalignment issue while maintaining the benefits of split-bit readout.
2Measurement precision
If more ADCs are placed on the ROIC to increase digital resolution, then digital resolution is improved, but device complexity and manufacturing difficulty increase
Solution Approach 1:
The patent applies segmentation by dividing the digital readout into two separate components: an in-pixel counter that captures the most significant bits (MSBs) and an ADC that captures the least significant bits (LSBs). This segmentation allows each component to be optimized independently - the counter provides high-resolution coarse measurement while the ADC provides fine-grained precision measurement. The segmented approach reduces the burden on any single ADC, lowering device complexity while maintaining high overall digital resolution through the combined 12-bit output.
Data Source
AI summary
In accordance with various embodiments of the disclosed subject matter, a system, device, apparatus and method for calibrating a split bit digital readout to avoid misalignment of the least significant counter bit (i.e., the LSB of the M most significant bits) and most significant residual bit (i.e. the MSB of the N least significant bits). For example, various embodiments provide a field programmable gate array (FPGA), digital signal processing (DSP) function and the like configured to calibrate one or many split bit digital readouts such as may exist on a digital pixel sensor (DPS) or other device.