Split-Body Super Junction FET Using Seven-Mask Fabrication
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Solution Overview
Problem
Conventional power N-channel field effect transistors face challenges in achieving low drain-to-source resistance and high breakdown voltage requirements, leading to large die sizes and increased costs, while super junction techniques can reduce die size but require improvements for efficient manufacturing.
Innovation Solution
A split-body Super Junction Field Effect Transistor (FET) device with a charge compensation region composed of alternating P− type and N− type epitaxial semiconductor columns, featuring a higher concentration of N type dopants in the upper portion and a novel semiconductor fabrication process using seven masks, including deep trench, polysilicon, and metal masks, to create a smaller and more cost-effective transistor.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the concentration of N type dopants in the N type drift region is reduced to achieve high breakdown voltage, then the breakdown voltage requirement is met, but the resistivity of the semiconductor material in the drift region increases undesirably
Solution Approach 1:
The drift region is segmented into multiple alternating P-type and N-type columns (charge compensation regions), where the P-type columns compensate for the low doping concentration in the N-type drift region, enabling high breakdown voltage while maintaining low resistivity through the segmented structure
Solution Approach 2:
The drift region uses a composite structure of alternating P-type and N-type semiconductor columns, creating a superjunction structure that combines the benefits of both doping types to achieve simultaneously high breakdown voltage and low resistivity
2Manufacturing precision
If the die area is increased to achieve the required low drain-to-source resistance RDS(ON), then the current rating requirement is met, but the manufacturing cost increases
Solution Approach 1:
The segmentation of the drift region into charge compensation columns enables a more efficient use of the die area, allowing the transistor to achieve the required current rating and low RDS(ON) with a smaller die size, thereby reducing manufacturing cost
3Area of stationary object
If super junction techniques are employed to reduce die size, then the die area is reduced for the same breakdown voltage and current rating, but manufacturing process complexity increases
Solution Approach 1:
The segmented columnar structure of the superjunction is formed through a systematic fabrication process using seven masks, where each mask step creates specific patterns that self-align to form the alternating P-N columns, managing the complexity through structured patterning
Solution Approach 2:
The fabrication process uses nested patterning steps where subsequent mask steps build upon previous patterns, with the seven masks creating increasingly complex structures in a hierarchical manner that manages overall process complexity
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution enables the production of smaller, cost-effective power transistors that meet breakdown voltage and current rating requirements by optimizing the charge compensation region and fabrication process, improving the performance and efficiency of Super Junction FETs.
Implementation Method 1
the drift region includes what is called a 'charge compensation region'. For the same required breakdown voltage, and for the same required current rating, the die of the Super Junction N-channel field effect transistor can be made smaller than if a conventional transistor architecture were employed.
Implementation Method 2
no P type dopants for the floating rings are implanted through the ILD layer or through holes in the ILD layer
Data Source
AI summary
A split-body Super Junction FET is made using only seven masks. Thin oxide is disposed on an upper semiconductor surface of a super junction charge compensation region. A polysilicon gate is disposed on the thin oxide. An ILD (InterLayer Dielectric) layer is disposed on the upper surface of the thin oxide so that the ILD layer covers the polysilicon gate. A gate bus line metal structure and a field plate metal structure are disposed on the upper surface of the ILD. A portion of the upper surface of the ILD extends from the gate bus line metal, laterally over floating rings, and to the field plate metal. This portion of the upper surface of the ILD layer is substantially planar where the ILD layer passes over the floating rings. The field plate metal structure, a polysilicon feature, and a diffusion region together form a stepped depletion layer field plate structure.