Split-Body Transistor Gate Structure for Leakage Reduction
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Solution Overview
Problem
Conventional transistors with semiconductor materials exhibit high off-current, affecting charge retention and electrical properties, and dual-gate electrodes are inadequate to reduce leakage as memory cells are scaled down, leading to increased coupling capacitance between neighboring transistors.
Innovation Solution
The use of transistors with a single gate electrode surrounding three sides of two channel regions, allowing for a larger gate thickness and reduced electrical resistance, and the inclusion of an electrically conductive shielding material between transistors to prevent wordline disturb, while maintaining the same pitch as conventional transistors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional semiconductor materials are used in transistors, then the transistors can conduct current when threshold voltage is applied, but they exhibit high off current that affects charge retention and neighboring transistors
Solution Approach 1:
The channel region is divided into two separate channel regions (first channel region and second channel region) that are spatially separated by the gate electrode. This segmentation reduces the coupling capacitance between adjacent transistors and lowers the off current that affects neighboring devices, while maintaining proper charge retention in each channel region.
2Reliability
If dual-gate electrodes are used around a central channel region, then gate control is improved, but leakage is not adequately reduced as memory cells are scaled down due to coupling capacitance between horizontally neighboring transistors
Solution Approach 1:
Instead of using a dual-gate configuration around a central channel, the invention segments the channel into two separate channel regions with a single gate electrode positioned between them. This segmentation approach achieves leakage reduction by increasing spatial separation between adjacent transistor channels, thereby reducing coupling capacitance without requiring complex dual-gate structures.
3Productivity
If memory cells are scaled down to increase density, then device density is improved, but coupling capacitance between horizontally neighboring transistors increases leading to increased leakage
Solution Approach 1:
The invention transitions from a horizontal arrangement where channels are adjacent to each other to a vertical arrangement where two channel regions are stacked with the gate electrode between them. This dimensional change allows for reduced coupling capacitance while maintaining high density, as the vertical separation provides better isolation between channels compared to horizontal placement at scaled dimensions.
4Reliability
If a single gate electrode is positioned between two channel regions, then gate area is increased reducing electrical resistance, but the transistor structure becomes more complex
Solution Approach 1:
The single gate electrode positioned between the two channel regions serves multiple functions: it controls both channel regions simultaneously, provides electrical isolation between the channels to reduce coupling capacitance, and its increased area reduces electrical resistance. This multi-functional design achieves multiple performance improvements without proportionally increasing device complexity.
Data Source
AI summary
An apparatus comprises a first conductive structure and at least one transistor in electrical communication with the first conductive structure. The at least one transistor comprises a lower conductive contact coupled to the first conductive structure and a split-body channel on the lower conductive contact. The split-body channel comprises a first semiconductive pillar and a second semiconductive pillar horizontally neighboring the first semiconductive pillar. The at least one transistor also comprises a gate structure horizontally interposed between the first semiconductive pillar and the second semiconductive pillar of the split-body channel and an upper conductive contact vertically overlying the gate structure and coupled to the split-body channel. Portions of the gate structure surround three sides of each of the first semiconductive pillar and the second semiconductive pillar. Memory devices, electronic systems, and methods of forming the apparatus are also disclosed.