Split Bottom Metallization for Low Resistivity Interconnects
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Solution Overview
Problem
In integrated circuits with minimum feature sizes of 30 nm to 40 nm, the dimensions of metal lines are scaled down, leading to increased resistivity and RC delay due to copper interconnects approaching the mean free path of electrons, and copper voids become a significant issue, which conventional interconnect formation schemes cannot address by increasing metal line width.
Innovation Solution
The metallization layers are divided into a first and a second M1 layer, with metal lines in each layer having widths greater than the minimum feature size, and vias connecting them, allowing for improved pitches and widths, reducing resistivity and RC delay.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If the dimensions of metal lines are scaled down to match the minimum feature size (30 nm to 40 nm), then the area occupied by the memory is reduced, but the resistivity of the interconnect structure significantly increases
Solution Approach 1:
The patent divides the bottom metallization layer into multiple sub-layers (first M1 layer and second M1 layer), allowing metal lines to be segmented across different layers. This segmentation enables the use of wider metal lines in each sub-layer while maintaining the overall compact layout, thereby reducing resistivity without increasing the total memory area.
Solution Approach 2:
The patent transitions from a single-plane metallization approach to a multi-layer metallization structure. By adding the vertical dimension with multiple M1 layers, the design achieves wider effective metal line widths and larger pitches without increasing the planar footprint, thus reducing resistivity while maintaining area efficiency.
2Reliability
If the width of metal lines is increased to reduce resistivity, then the RC delay in the interconnect structure is reduced, but the area occupied by the memory increases
Solution Approach 1:
The patent segments the metallization function across multiple M1 layers, allowing each layer to carry portions of the interconnect network. This enables wider metal lines with lower RC delay in each layer while the overall memory area remains compact due to the efficient vertical stacking of these segmented interconnect paths.
Solution Approach 2:
By utilizing the vertical dimension through multiple metallization layers, the patent achieves wider effective metal line widths that reduce RC delay, while the planar area remains minimized because the additional interconnect capacity is achieved through layer stacking rather than lateral expansion.
3Ease of manufacture
If copper is filled into via openings and trench openings at 30 nm and 40 nm technologies, then the interconnect structure is formed, but copper voids become a major problem
Solution Approach 1:
The patent segments the copper filling process into multiple stages corresponding to different M1 layers. Each layer can be filled and planarized separately, allowing better control over copper deposition and reducing the formation of voids that commonly occur in single-step high-aspect-ratio filling processes at 30 nm and 40 nm nodes.
Solution Approach 2:
The patent performs preliminary planarization and copper filling for each M1 layer before proceeding to the next layer. This staged approach allows each copper fill operation to occur in a controlled, shallower trench environment, preventing void formation that would result from attempting to fill deep, high-aspect-ratio trenches in a single operation.
4Reliability
If the pitch and width of metal lines are increased beyond the minimum feature size, then the resistivity is reduced, but the conventional interconnect formation schemes cannot accommodate this increase
Solution Approach 1:
The patent segments the bottom metallization function into multiple M1 layers, each with its own set of metal lines having increased pitch and width. This segmentation allows each layer to use relaxed design rules with larger dimensions for lower resistivity, while the overall system complexity is managed through the modular, repetitive structure of the segmented layers.
Data Source
AI summary
An integrated circuit structure includes a semiconductor substrate; a first bottom metallization (M1) layer over the semiconductor substrate; a second M1 layer over the first M1 layer, wherein metal lines in the first and the second M1 layer have widths of greater than about a minimum feature size; and vias connecting the first and the second M1 layers.