Split-Buffer LDO Regulator for Fast Transient Response
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Solution Overview
Problem
Existing low-dropout (LDO) voltage regulators face challenges in achieving fast load transient response without incurring high no-load quiescent current, particularly due to the high capacitance of the pass circuit control node.
Innovation Solution
The implementation of a split-buffer stage architecture in the LDO voltage regulator, where a first buffer circuit drives the pass circuit and a second buffer circuit drives a sense circuit, creates a feedforward path that bypasses the high-capacitance pass circuit control node, allowing for adaptive biasing without increasing no-load quiescent current.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Strength
If a large power FET is used for the pass element to allow very low dropout operation, then the dropout voltage is reduced, but the gate-to-source capacitance and Miller capacitance increase, requiring higher quiescent current to drive the gate driver
Solution Approach 1:
The single buffer stage is segmented into two separate buffer stages: a first buffer stage that drives the pass element gate, and a second buffer stage that drives the sense amplifier. This segmentation allows each buffer to be optimized independently, with the first buffer providing sufficient drive capability for fast transient response while the second buffer handles sensing operations, thereby reducing the overall quiescent current requirement compared to a single high-current buffer
Solution Approach 2:
The sense amplifier acts as an intermediary between the second buffer stage and the feedback control, providing voltage sensing and comparison functionality. This intermediary stage enables the system to achieve fast transient response through proper compensation and control without requiring the pass element gate driver to operate at excessively high current levels
2Loss of time
If a high fixed current bias source is used to drive the power FET at no-load, then the propagation delay is reduced, but the no-load quiescent current increases significantly
Solution Approach 1:
The bias current for the first buffer stage is made dynamic rather than fixed, allowing it to adapt to loading conditions. The buffer stages are designed to provide sufficient current during transient events while consuming minimal current during no-load operation, achieving fast propagation delay only when needed without the penalty of continuously high quiescent current
Solution Approach 2:
The operating parameters of the buffer stages, particularly the bias current levels, are optimized to change based on operational requirements. The circuit transitions between different current states depending on load conditions, enabling fast response times during transients while maintaining low quiescent current during steady-state no-load operation
3Device complexity
If a single buffer stage is used to drive both the pass element and sense amplifier, then the device complexity is reduced, but the load transient response performance deteriorates due to the high capacitance of the pass circuit control node
Solution Approach 1:
The control architecture is segmented into two independent buffer stages, each optimized for its specific function. The first buffer stage is dedicated to driving the pass element gate with sufficient current capability for fast switching, while the second buffer stage drives the sense amplifier with appropriate impedance matching. This segmentation resolves the bottleneck caused by the high capacitance of the pass circuit control node by providing dedicated drive capability without requiring excessive complexity
Data Source
AI summary
Techniques are described herein for regulating output voltage using a low-dropout (LDO) voltage regulator. In an example, an LDO voltage regulator circuit includes a pass circuit that is driven or otherwise controlled by a first buffer circuit, and a sense circuit that is driven or otherwise controlled by a second buffer circuit. The pass circuit is configured to pass current from a voltage supply terminal to an output voltage terminal, responsive to a first control signal. The sense circuit is configured to sense the current passed by the pass circuit, responsive to a second control signal. The first buffer circuit is configured to provide the first control signal to the pass circuit, responsive to a third control signal, and the second buffer circuit is configured to provide the second control signal to the pass circuit, also responsive to the third control signal.