Split Capacitor DAC Layout for Linear SAR ADC Conversion
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Solution Overview
Problem
Successive approximation AD converters with capacitance array type DACs face issues with mismatch precision due to parasitic capacitance, leading to nonlinear AD conversion characteristics and increased area and power consumption, especially when trying to correct for offset in the comparator.
Innovation Solution
Incorporating a capacitance DAC with a higher-order and lower-order part connected by a coupling capacitor, and using variable capacitive elements in the lower-order part to adjust capacitance values, allowing for correction of capacitance mismatch and parasitic capacitance effects through a higher-order DAC control circuit and correction control signals.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a capacitance array type DAC is used for successive approximation AD conversion, then multi-bit analog-to-digital conversion can be achieved, but the capacitance value increases with higher-order bits causing increased area and power consumption
Solution Approach 1:
The capacitance array is divided into multiple groups, with each group handling specific bit ranges. The first group handles higher-order bits while the second group handles lower-order bits, allowing independent optimization of each segment's capacitance values to reduce overall area while maintaining conversion precision.
Solution Approach 2:
Different capacitance values are assigned to different groups of capacitive elements based on their bit significance. The capacitance values in the first group are optimized for higher-order bits while the second group uses different values for lower-order bits, enabling parameter optimization that reduces total area without sacrificing measurement precision.
2Manufacturing precision
If capacitance values are increased to correct for parasitic capacitance and improve mismatch precision, then AD conversion linearity improves, but area and power consumption increase
Solution Approach 1:
The capacitance array is segmented into multiple groups that can be independently controlled. This segmentation allows parasitic capacitance compensation to be applied selectively to specific groups rather than requiring uniform increases across all capacitors, thereby improving mismatch precision without proportionally increasing power consumption.
Solution Approach 2:
Different capacitance compensation strategies are applied to different groups based on their specific requirements. The first group receives compensation tailored to its higher-order bit function while the second group receives compensation suited to its lower-order bit function, optimizing precision locally without unnecessary power consumption increases.
3Area of stationary object
If the capacitance array is divided into higher-order and lower-order parts with a coupling capacitor, then capacitance values for higher-order bits are reduced, but mismatch precision deteriorates due to parasitic capacitance
Solution Approach 1:
A feedback mechanism is introduced where the output of the second group is fed back to the input of the first group through the coupling capacitor. This feedback loop enables dynamic compensation for parasitic capacitance effects, maintaining mismatch precision despite the physical division and area reduction of the capacitance array.
Solution Approach 2:
The coupling capacitor acts as an intermediary element between the first and second groups. It not only connects the two groups but also serves as a feedback path that compensates for parasitic capacitance, thereby maintaining precision while allowing the capacitance array to be divided for area reduction.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration improves mismatch precision, enables high-precision AD conversion with linear characteristics, and reduces power consumption by correcting capacitance weighting errors, even when an offset is present in the comparator.
Implementation Method 1
a coupling capacitor configured to connect the first common node and the second common node
Implementation Method 2
Successive approximation AD converters with capacitance array type DACs face issues with mismatch precision due to parasitic capacitance
Data Source
AI summary
A higher-order DAC and a lower-order DAC each have a plurality of capacitive elements having capacitance values weighted with a binary ratio and are configured so that a first terminal of each of the capacitive elements is connected to a common node and a second terminal thereof is connected to either a first or second voltage selectively. The higher-order DAC and the lower-order DAC are coupled by a coupling capacitor. A higher-order DAC control circuit outputs either a correction control signal or a digital signal output from a successive approximation circuit selectively to the higher-order DAC. The lower-order DAC has at least one variable capacitive element of which a first terminal is connected to the common node and a second terminal is connected to either the first or second voltage selectively depending on a higher-order bit of the digital signal output from the successive approximation circuit to the higher-order DAC.