Split Capacitor SAR ADC Layout for Lower Input Capacitance
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Solution Overview
Problem
High-bit-resolution SAR ADC converters face challenges due to exponentially increasing input capacitance and silicon area requirements, making them impractical as the ratio between the MSB and LSB capacitors becomes too large.
Innovation Solution
The implementation of a split capacitor array with a coupling capacitor between two nodes and a trimmable grounded capacitor, dividing the capacitors into LSB and MSB arrays, reducing total input capacitance and silicon area, and allowing for easier trimming to achieve a unit capacitance value.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If binary weighted capacitor array is used for high-bit-resolution SAR ADC, then conversion precision is improved, but input capacitance and silicon area increase exponentially
Solution Approach 1:
The capacitor array is divided into two separate arrays: an LSB capacitor array and an MSB capacitor array. The LSB array contains capacitors with smaller capacitance values while the MSB array contains capacitors with larger capacitance values. This segmentation allows each array to be optimized independently, reducing the total input capacitance while maintaining the required conversion precision for high-bit-resolution SAR ADC.
2Measurement precision
If binary weighted capacitor array is used for high-bit-resolution SAR ADC, then conversion precision is improved, but silicon area increases exponentially
Solution Approach 1:
The capacitor array is divided into two separate arrays: an LSB capacitor array and an MSB capacitor array. The LSB array contains capacitors with smaller capacitance values while the MSB array contains capacitors with larger capacitance values. This segmentation allows each array to be optimized independently, reducing the total silicon area required while maintaining the required conversion precision for high-bit-resolution SAR ADC.
3Measurement precision
If large ratio between MSB and LSB capacitors is used, then conversion precision is improved, but ease of manufacture deteriorates
Solution Approach 1:
The capacitor array is divided into two separate arrays: an LSB capacitor array and an MSB capacitor array. This segmentation reduces the capacitance ratio within each array, making trimming and manufacturing more manageable while maintaining overall conversion precision.
Solution Approach 2:
A coupling capacitor is introduced as an intermediary element between the LSB and MSB capacitor arrays. This coupling capacitor facilitates the interaction between the two arrays and enables precise control of the overall capacitance ratio, improving ease of manufacture and trimming while maintaining conversion precision.
Data Source
AI summary
An array of capacitors includes a first array of k capacitors coupled to a first node and having capacitances which are binary weighted multiples of a unit capacitance value, a second array of m capacitors coupled to a second node and having capacitances which are binary weighted multiples of the unit capacitance value, a coupling capacitor disposed between the first node and the second node, and a trimmable grounded capacitor coupled between the first node and a ground potential.