3D Memory Channel Structure With Overlapping Source Line Layout
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Solution Overview
Problem
The manufacturing process of three-dimensional semiconductor memory devices is complex compared to two-dimensional devices, due to the intricate arrangement of memory cells.
Innovation Solution
A semiconductor memory device is designed with a substrate having a CMOS circuit, a gate stack structure with interlayer insulating layers and conductive patterns, a channel structure with a first part penetrating the gate stack and a second part extending beyond it, a common source line overlapping with the gate stack, a memory layer between the channel and gate stack, and a bit line connected to the channel structure.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory cells are three-dimensionally arranged to improve integration density, then the degree of integration increases, but the manufacturing process complexity increases
Solution Approach 1:
The channel structure is divided into two distinct parts: a first part that penetrates the gate stack structure and a second part that extends beyond it. This segmentation allows different portions of the channel to be formed and processed at different stages, simplifying the overall manufacturing process while maintaining three-dimensional integration
Solution Approach 2:
The first part of the channel structure is formed to penetrate the gate stack structure before the gate stack is fully completed. This preliminary action allows subsequent processing steps to work around the existing channel structure, reducing the complexity of forming three-dimensional intersections
2Quantity of substance
If the channel structure penetrates the gate stack structure to achieve three-dimensional arrangement, then the memory cell integration improves, but the structural complexity increases
Solution Approach 1:
The channel structure is divided into two distinct parts: a first part that penetrates the gate stack structure and a second part that extends beyond it. This segmentation allows different portions of the channel to be formed and processed at different stages, simplifying the overall manufacturing process while maintaining three-dimensional integration
Solution Approach 2:
The channel structure extends in multiple dimensions: vertically through the gate stack (first part) and horizontally beyond it (second part). This multi-dimensional arrangement enables three-dimensional memory cell integration while maintaining a relatively simple structural configuration that can be manufactured using standard semiconductor processing techniques
Data Source
AI summary
There is provided a semiconductor memory device including: a substrate having a Complementary Metal Oxide Semiconductor (CMOS) circuit; a gate stack structure including interlayer insulating layers and conductive patterns, which are alternately stacked in a vertical direction on the substrate; a channel structure having a first part penetrating the gate stack structure and a second part extending from one end of the first part, the second part extending beyond the gate stack structure; a common source line extending to overlap with the gate stack structure, the common source line surrounding the second part of the channel structure; a memory layer disposed between the first part of the channel structure and the gate stack structure; and a bit line connected to the other end of the first part of the channel structure, the bit line being disposed between the substrate and the gate stack structure.