Split-Chip SerDes Interface for SoC Noise and Die Area Limits
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Solution Overview
Problem
The design of serializer-deserializer (SerDes) interfaces in system-on-a-chip (SoC) integrated circuits becomes increasingly challenging at advanced technology nodes due to noise sensitivity, voltage headroom issues, and the need for high-precision clocks, leading to design bottlenecks and increased die area and cost.
Innovation Solution
The SerDes interface is segregated into a separate SerDes interface die, allowing the SoC to evolve independently of the SerDes design, with the SoC and SerDes integrated into a single package, enabling control over internal transmission channel characteristics to simplify the PHY interfaces and reduce design complexity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If SerDes interface is integrated into SoC, then functionality is complete, but design complexity and die area increase
Solution Approach 1:
The SerDes interface is segmented from the SoC into a separate integrated circuit. The SoC includes a first SerDes interface for internal communication, while the separate IC includes a second SerDes interface for external communication, allowing independent design and optimization of each component.
Solution Approach 2:
The complex analog SerDes components (transmitter, receiver, PLL, equalizer) are extracted from the SoC and placed in a dedicated integrated circuit. This extraction reduces the SoC's design complexity and die area while maintaining full SerDes functionality through the separate IC.
2Adaptability or versatility
If SerDes interface is integrated into SoC, then functionality is complete, but die area and cost increase
Solution Approach 1:
The SerDes functionality is segmented into a separate integrated circuit, allowing the SoC to retain only essential digital components while the analog SerDes components occupy dedicated silicon real estate in the separate IC, thereby optimizing die area utilization.
Solution Approach 2:
The large-area analog components (transmitter, receiver, PLL, equalizer) are extracted from the SoC die to a separate IC. This extraction significantly reduces the SoC's die area requirement while maintaining complete SerDes functionality through the separate component.
3Reliability
If SerDes interface is integrated into SoC, then signal integrity is maintained, but noise sensitivity and voltage headroom issues worsen
Solution Approach 1:
A dedicated integrated circuit serves as an intermediary between the SoC and external SerDes interfaces. This intermediary contains specialized analog components optimized for high-speed serial communication, providing galvanic isolation and dedicated signal paths that reduce noise sensitivity and improve signal integrity.
Solution Approach 2:
The separate integrated circuit provides localized high-quality analog signal processing with dedicated power domains and shielding for the transmitter, receiver, and PLL components. This local quality optimization reduces noise sensitivity and improves voltage headroom management for critical SerDes functions.
Data Source
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AI summary
An SoC integrated circuit package is provided in which the analog components of a SerDes for an SoC die in the SoC integrated circuit package are segregated into a SerDes interface die in the SoC integrated circuit package.