Split Flip-Flop Clocks With Programmable Setup-Time Delay
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Solution Overview
Problem
Existing electronic circuits face limitations in operational frequency and performance due to setup time and clock-to-output (C2Q) delays, clock skew, and jitter, which are not adequately addressed by prior methods, especially in post-silicon conditions where fabrication variations and temperature/voltage changes affect clock cycle periods.
Innovation Solution
A clock distribution system with split clocks and a master clock gating circuit that generates a master clock signal different from the slave clock signal, allowing for a programmable delay to be introduced, enabling more computation time in timing paths without increasing the clock cycle time by separating the clock signals for master and slave latches in flip-flop circuits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a fixed setup and hold time is used for sequential elements with a grid system for clock distribution, then clock skew and jitter are reduced to negligible amounts, but setup time and C2Q delay still limit the operational frequency
Solution Approach 1:
The patent applies dynamics by making the clock distribution system adjustable and adaptive. Instead of a fixed grid system, the invention introduces a programmable clock distribution mechanism that can dynamically adjust clock timing parameters (such as clock-to-output delay) based on actual timing path requirements. This allows the system to optimize for both skew reduction and frequency improvement by adapting to different operational conditions and timing constraints.
2Productivity
If a programmable delayed clock is provided to a flip-flop in post-silicon to decrease setup time, then the clock cycle period decreases and operational frequency increases, but the C2Q delay of the subsequent timing path increases
Solution Approach 1:
The patent applies local quality by providing different clock timing characteristics to different parts of the circuit. Specifically, it introduces selective clock delay adjustment where only certain flip-flops receive delayed clock signals based on their specific timing path requirements. This localized adjustment allows setup time optimization for critical paths without unnecessarily increasing C2Q delay for all subsequent paths, as the delay is applied selectively rather than globally.
Solution Approach 2:
The invention segments the clock distribution into multiple independent controllable paths. Instead of a unified clock distribution system, it divides the clock network into segments that can be independently adjusted. This segmentation allows different timing parameters to be applied to different timing paths, enabling optimization of setup time for one path without adversely affecting C2Q delay in other paths.
3Ease of manufacture
If pre-silicon software models are used to approximate fabrication process effects, then clock skew and jitter analysis can be performed before die fabrication, but variations in models from real behavior and post-silicon temperature and voltage variations cause skew value to increase
Solution Approach 1:
The patent applies feedback by implementing a post-silicon measurement and adjustment mechanism. The system measures actual clock skew and timing parameters after fabrication and uses this feedback to programmably adjust the clock distribution timing. This closed-loop approach compensates for the inaccuracies in pre-silicon models and post-silicon environmental variations, allowing the system to achieve accurate skew control despite the limitations of pre-silicon analysis.
Data Source
AI summary
A system and method for efficient improvement of timing analysis for faster processor designs with negligible impact on die-area. Rather than provide a single clock to flip-flop circuits on a semiconductor chip, split clocks are used. A flip-flop receives a master clock signal for a master latch and receives a separate slave clock signal for a slave latch. Master and slave clock gater circuits are coupled to a global clock distribution system and the local flip-flops. The master clock gater circuit receives a delay control signal used to select a delay, wherein the selected delay determines an additional amount of time the master clock signal transitions after the slave clock signal transitions. The use of the delayed master clock on the semiconductor chip may allow a timing path to have more computation time without increasing the clock cycle time. Further, the delay may be chosen to fix timing paths in post-silicon.