Split Conductive Pad for IC Package Routing
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Solution Overview
Problem
Integrated circuit (IC) packages face challenges in routing conductive traces due to large conductive pads, which restrict layout options and lead to parasitic impedance, crosstalk, and power distribution issues, especially when coupling surface-mount components with terminals that have not decreased in size proportionally.
Innovation Solution
The implementation of split conductive pads, which are physically separated but electrically coupled, allows for more efficient conductive trace routing, improved signal integrity by reducing bends and crosstalk, and enhanced power integrity by increasing connection space for voltage and ground reference rails.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If large conductive pads are used to couple surface-mount components, then connection reliability is improved, but layout flexibility deteriorates and parasitic impedance increases
Solution Approach 1:
The conductive pad is divided into multiple separate pad segments (first conductive pad, second conductive pad, third conductive pad, fourth conductive pad) instead of using a single large pad. These segments are electrically connected through conductive traces, allowing the signal to be routed through multiple smaller contact points rather than one large pad, thereby improving layout flexibility while maintaining connection reliability.
Solution Approach 2:
The patent transitions from a two-dimensional pad layout to a three-dimensional routing structure by introducing conductive traces that connect pad segments vertically and horizontally across multiple layers. This allows the signal path to extend in the Z-dimension (through vias) and across multiple copper layers, effectively increasing the connection surface area and reliability without expanding the footprint on any single layer.
2Reliability
If large conductive pads are used, then connection space is increased, but parasitic impedance and crosstalk increase
Solution Approach 1:
By segmenting the large conductive pad into multiple smaller pad segments connected by traces, the patent reduces the parasitic capacitance associated with large continuous conductive areas. The smaller pad segments have reduced self-capacitance, and the distributed trace routing reduces inductive effects, thereby lowering overall parasitic impedance while maintaining adequate connection space through multi-layer routing.
Solution Approach 2:
Conductive traces serve as intermediaries between the pad segments, providing controlled impedance pathways that are designed to minimize signal degradation. The traces are routed through multiple layers with proper grounding and shielding, acting as mediators that reduce crosstalk and electromagnetic interference between adjacent signal paths.
3Productivity
If electrical components are mounted on-die, then integration density is improved, but manufacturing complexity increases
Solution Approach 1:
The patent segments the integration approach by keeping passive components as separate surface-mount devices rather than integrating them directly onto the die. The conductive pad segments and multi-layer traces provide a compact routing solution that achieves high integration density while maintaining the manufacturing simplicity of separate component assembly through standard PCB fabrication processes.
4Device complexity
If conductive traces are routed through large pads, then layout options are restricted, but signal integrity deteriorates
Solution Approach 1:
Segmenting the pads into multiple smaller units connected by traces creates additional routing options where signals can travel through vertical vias and across multiple copper layers. This segmentation allows traces to be routed around obstacles and through optimized paths, improving signal integrity by avoiding direct routing through large discontinuous pad areas while providing multiple layout configurations.
Solution Approach 2:
By utilizing multiple PCB layers and vertical vias, the patent adds the Z-dimension to trace routing, allowing signals to bypass obstacles on any given layer and providing three-dimensional routing flexibility. This multi-layer approach improves signal integrity by enabling controlled impedance routing and proper grounding practices while dramatically increasing the number of available layout options.
Data Source
AI summary
Certain aspects of the present disclosure generally relate to a chip package having a split conductive pad for coupling to a device terminal. An example chip package generally includes a layer, a first plurality of conductive pads disposed on the layer, at least one conductive trace disposed on the layer and between the first plurality of conductive pads, and an electrical component having a first terminal coupled to the first plurality of conductive pads and disposed above the at least one conductive trace.