Split-Counter Phase Accumulator for Low-Power PLL Phase Measurement
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Solution Overview
Problem
Conventional Phase-Locked Loops (PLLs) face challenges in achieving high speed, accuracy, large range, low jitter, and low power simultaneously, particularly in deep-submicron integrated circuit technologies, due to limitations in phase accumulator design and oscillator frequency control.
Innovation Solution
The proposed PLL architecture includes a split counter and latch design, a phase accumulator with a delay line and calibrator, and a binary encoder to improve phase measurement accuracy and reduce power consumption, along with a beat-frequency operation method to optimize frequency lock ranges and reduce power usage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a conventional phase accumulator design is used to achieve high speed and large range, then the PLL can operate at high frequencies with wide frequency ranges, but power consumption increases significantly
Solution Approach 1:
The phase accumulator is divided into two independent counters: a first counter that accumulates phase values at high speed with a wider counting range, and a second counter that accumulates at lower speed with a narrower range. This segmentation allows the system to achieve high-speed operation when needed while consuming less power during normal operation, as the lower-speed counter can handle routine phase accumulation tasks.
2Device complexity
If a single counter design is used, then the circuit is simple, but it cannot simultaneously achieve high speed, large range, and low power consumption
Solution Approach 1:
The system dynamically switches between the first and second counters based on operational requirements. The controller selectively activates which counter to use, allowing the phase accumulator to adapt its performance characteristics (speed, range, power consumption) to match the current operational demands, thereby achieving high productivity without excessive complexity.
3Measurement precision
If a conventional PLL architecture is used, then the design is straightforward, but it cannot achieve high accuracy, low jitter, and low power simultaneously
Solution Approach 1:
The system applies different operational characteristics to different parts of the phase accumulation process. The first counter is optimized for high-precision measurements with wider range, while the second counter handles lower-precision tasks with reduced power consumption. This local differentiation of quality allows the PLL to achieve high accuracy when needed without maintaining high power consumption continuously.
Data Source
AI summary
A PLL includes a controlled oscillator, a phase accumulator to measure the controlled oscillator output phase, a phase predictor to calculate the required output phase, and a phase subtractor to calculate the phase difference or phase error. The phase accumulator includes a fast counter and a low-power counter, and two sets of corresponding latches. The fast counter counts cycles of the controlled oscillator clock signal, and the low-power counter counts carry signals from the fast counter. The low-power counter represents one or more most significant bits of the integer part of the measured phase, and the fast counter represents the remaining bits. The phase accumulator may further include a delay line, second latches, and a delay line decoder to measure a fractional part of the phase. A calibration feedback loop may keep the number of delay line steps per output clock pulse known and stable.