Split Crossbar Circuit for Operand Routing in Computer Processors
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Computer processors face challenges in efficiently managing transient operands due to the limitations of general register machines, including increased complexity, entropy, and power requirements, as well as the sequential nature of accumulator and stack machines, which hinder parallel execution and instruction encoding density.
Innovation Solution
A computer processing system with a plurality of functional units and an interconnect network featuring first and second crossbar parts to route result operands based on characteristic latencies, allowing for separate result registers for each latency, enabling efficient transfer and storage of operands across multiple cycles.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the number of registers is increased to hold more transient operands, then the speed of the program is improved by avoiding memory access, but the instruction entropy and hardware complexity increase
Solution Approach 1:
The patent divides the register file into multiple banks (first register bank, second register bank, third register bank) that can be accessed independently and simultaneously. This segmentation allows multiple read/write operations to proceed in parallel, improving execution speed without proportionally increasing the complexity of a single monolithic register file. Each bank can be managed separately, reducing control logic complexity.
Solution Approach 2:
The patent introduces a bank selection dimension to the register addressing scheme. Instead of simply increasing the number of addresses in a single register file, it adds a spatial dimension by organizing registers into multiple banks that can be selected and accessed independently. This allows more operands to be held and accessed quickly without linearly increasing the address bus width or control complexity.
2Speed
If the number of registers is increased to hold more transient operands, then the speed of the program is improved by avoiding memory access, but the instruction encoding size increases
Solution Approach 1:
The register addressing space is segmented into bank identifiers and offset identifiers. This allows the instruction encoding to include a bank field and an offset field separately, enabling access to a large number of registers without requiring a single large address field. The segmented encoding maintains instruction compactness while providing access to more register resources.
Solution Approach 2:
The register banks are designed to be functionally equivalent and interchangeable, with each bank capable of holding transient operands. The universal bank structure allows the same encoding pattern to access any bank, reducing the need for special-case encoding and maintaining instruction encoding density while supporting a large total register count.
3Productivity
If multiple crossbar parts are used to route operands based on latency, then the processing efficiency is improved, but the interconnect network complexity increases
Solution Approach 1:
The interconnect network is segmented into multiple crossbar parts, each handling specific latency categories of operands. This segmentation allows each crossbar to be optimized for its specific function and size, reducing the complexity of individual crossbars compared to a single large crossbar. The modular structure makes the overall system more manageable despite the increased total complexity.
Solution Approach 2:
The system performs preliminary classification of operands by their latency characteristics before routing them through the interconnect network. By pre-categorizing operands into different latency groups and directing them to appropriate crossbar parts, the system avoids the need for complex dynamic routing decisions at each crossbar stage, simplifying the control logic of the interconnect network.
Data Source
AI summary
A computer processor including a plurality of functional units that performs operations that produce result operands at different characteristic latencies over multiple cycles. An interconnect network provides data paths for transfer of operand data between functional units. The interconnect network includes first and second crossbar parts. The first crossbar part is configured to route result operands produced with the lowest characteristic latency to any other functional unit. The second crossbar part is configured to route result operands with higher characteristic latency relative to the lowest characteristic latency to the first crossbar part where such result operands are in turn routed to any functional unit. In another aspect, the functional units can be organized as multiple slots where each slot can produce multiple result operands of different characteristic latencies in the same cycle, and wherein each slot employs separate result registers for each characteristic latency present on the slot.