Calibrated Split DAC Architecture for High Accuracy in Less Chip Area
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Solution Overview
Problem
Digital to analog converters face a tradeoff between accuracy and chip area, with high accuracy requiring significant space, and existing solutions struggle to provide precise conversion while minimizing the area allocated on an integrated circuit.
Innovation Solution
The method involves using a combination of a main digital to analog converter matched to 8 or 9 most significant bits and a 5-bit sub-DAC to reduce area, with the sub-DAC correcting errors and temperature variations, allowing for bit-by-bit calibration and digital domain corrections to maintain accuracy.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a high accuracy digital to analog converter is implemented, then conversion accuracy is improved, but chip area increases
Solution Approach 1:
The patent divides the DAC into two separate converters: a main DAC handling the most significant bits (MSBs) and a sub-DAC handling the least significant bits (LSBs). This segmentation allows each converter to be optimized for its specific function, with the sub-DAC being much smaller in area while the main DAC achieves acceptable accuracy for its bit range. The combined output of both converters achieves high overall accuracy without requiring a single large high-precision converter.
2Area of stationary object
If the chip area is reduced, then space allocation is improved, but conversion accuracy deteriorates
Solution Approach 1:
The patent implements a calibration mechanism where the output of the main DAC is measured and used to determine correction values that are applied to the sub-DAC. This feedback loop allows the system to compensate for inaccuracies in the main DAC, ensuring high overall conversion accuracy. The calibration process establishes correction values that adjust the sub-DAC output to match the ideal transfer function, maintaining precision despite the reduced area of individual components.
Data Source
AI summary
An input digital signal is converted to an analog signal using a main digital to analog converter (DAC) and a sub DAC. An offset value is subtracted from the input digital signal to generate an offset adjusted digital signal. The main DAC converts the offset adjusted digital signal to a first analog signal. A second digital signal is generated based on the offset value and a correction factor determined, at least in part, during calibration of the main DAC. The sub DAC converts the second digital to a second analog signal, which when combined with the first analog signal, provides an analog representation of the input digital signal.