Split Data Translation Lookaside Buffers for Processor Area Reduction
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Solution Overview
Problem
As processor core instructions per cycle increase, the existing unified data translation lookaside buffer (DTLB) faces challenges with area, complexity, and power consumption, necessitating a more efficient approach to handle load and store operations effectively.
Innovation Solution
The solution involves splitting the unified DTLB into separate load and store DTLBs, each with distinct sizes, associativity, replacement, and fill policies, allowing for independent operation and optimization of load and store operations, thereby reducing duplication and enhancing scalability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If a unified data translation lookaside buffer (DTLB) is used to handle both load and store operations, then the structure is simple and area is reduced, but the complexity of managing both operations in a single buffer increases and power consumption rises
Solution Approach 1:
The unified DTLB is segmented into two separate structures: a load DTLB for handling load operations and a store DTLB for handling store operations. Each DTLB can be independently sized and configured with appropriate associativity levels, allowing optimization for specific operation patterns while reducing the complexity of managing both operation types in a single buffer.
2Device complexity
If a unified DTLB handles both load and store operations, then device count is reduced, but power consumption increases due to maintaining current state for both operation types
Solution Approach 1:
By segmenting the unified DTLB into separate load and store DTLBs, each structure only needs to maintain state information relevant to its specific operation type. This reduces the total power consumption compared to a unified DTLB that must maintain and manage state for both load and store operations simultaneously.
3Productivity
If the DTLB is designed to handle increasing instructions per cycle, then processing capability improves, but area and power consumption increase
Solution Approach 1:
Segmentation allows each DTLB to be independently sized according to the specific bandwidth requirements of load and store operations. This enables scaling the total DTLB capacity to match actual workload demands without over-provisioning, thus supporting higher instructions per cycle while controlling area growth.
Solution Approach 2:
Different DTLBs can be configured with different associativity levels and sizes based on the local characteristics of load versus store workloads. This allows optimization for specific operation patterns without uniformly increasing the size of the entire translation buffer structure.
4Device complexity
If a unified DTLB is used, then device complexity is low, but adaptability to different operation patterns is reduced
Solution Approach 1:
The segmented architecture allows each DTLB to be independently configured with optimal associativity and size for its specific operation type. This provides adaptability to different load and store patterns while keeping each individual DTLB configuration relatively simple.
Solution Approach 2:
Each DTLB can be locally optimized for its specific operation pattern (load or store) with appropriate associativity and sizing, providing versatility in handling different workload characteristics without requiring complex unified management logic.
Data Source
AI summary
Systems, methods, and apparatuses relating to hardware for split data translation lookaside buffers. In one embodiment, a processor includes a decode circuit to decode instructions into decoded instructions, an execution circuit to execute the decoded instructions, and a memory circuit comprising a load data translation lookaside buffer circuit and a store data translation lookaside buffer circuit separate and distinct from the load data translation lookaside buffer circuit, wherein the memory circuit sends a memory access request of the instructions to the load data translation lookaside buffer circuit when the memory access request is a load data request and to the store data translation lookaside buffer circuit when the memory access request is a store data request to determine a physical address for a virtual address of the memory access request.