Split Decoder Compression for High-Rate Channel Output Decoding

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Solution Overview

Problem

High-speed data communications face a bottleneck due to the need for large data bus widths and high clock frequencies, which are costly and power-intensive, especially as user data rates increase beyond current silicon technology capabilities.

Innovation Solution

The implementation of syndrome decoding methods and data compression techniques, such as arithmetic coding, to reduce the complexity of communicating channel outputs from the receiver to the decoder, utilizing a split decoder architecture that optimizes the interface between the receiver and decoder without degrading frame error rate performance.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If the user data rate is increased to meet high-speed communication demands, then the data transmission capacity is improved, but the required data bus width and clock frequency increase, leading to higher cost and power consumption

Engineering Contradiction:
Improveuser data rateVSAvoiddata bus width
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The patent extracts only the essential information from channel outputs by computing syndromes, which are sufficient for error detection and correction. Instead of transferring all channel output data, only the compressed syndrome information is sent to the decoder, dramatically reducing data bus width requirements while maintaining high data rates

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The patent changes the representation parameter of channel information from raw channel outputs to syndrome values. This parameter transformation compresses the data significantly, allowing high user data rates to be achieved without proportionally increasing the data bus width, thus resolving the contradiction between productivity and device complexity

Inventive Principle:
Principle #35Parameter changes

2Speed

If the clock frequency is increased to handle high data rates, then the processing speed is improved, but the power consumption and implementation cost increase

Engineering Contradiction:
Improveprocessing speedVSAvoidpower consumption
Core Design Contradiction:
SpeedVSUse of energy by moving object

Solution Approach 1:

By extracting only syndrome information from channel outputs, the patent reduces the volume of data that needs to be processed at high clock frequencies. This allows the system to achieve high effective processing speed for useful information while operating at lower clock frequencies, thereby reducing power consumption

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The patent applies partial action by processing only the essential syndrome portion of channel information rather than all channel outputs. This selective processing reduces the computational burden and allows lower clock frequencies to achieve the same effective throughput, reducing power consumption

Inventive Principle:
Principle #16Partial or excessive action

3Device complexity

If syndrome decoding and compression techniques are applied to reduce data bus width, then the device complexity is reduced, but the frame error rate performance may be degraded

Engineering Contradiction:
Improvedata bus widthVSAvoidframe error rate
Core Design Contradiction:
Device complexityVSReliability

Solution Approach 1:

The patent introduces syndrome computation as an intermediary process between channel reception and decoding. The syndrome acts as a mediator that compresses channel information while preserving all essential error-detection and error-correction information, thus maintaining frame error rate performance despite reduced data bus width

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The patent creates a compressed copy of channel information in the form of syndromes. This syndrome copy contains all necessary information for accurate decoding and error correction, proving that full-resolution channel output data is not needed, thus maintaining reliability while reducing device complexity

Inventive Principle:
Principle #26Copying

Data Source

PatentEP3844883B1Method and system for decoding data using compressed channel output information
Publication Date: 2023.03.15 POLARAN HABERLESME TEKNOLOJILERI ANONIM SIRKETI
  • EP3844883B1 patent drawingFigure 1
  • EP3844883B1 patent drawingFigure 2
  • EP3844883B1 patent drawingFigure 3

AI summary

A split decoder apparatus 200, 400 in a communication system 100 provides reliable transfer of a transmitted message from a source to a destination. A channel encoder 110 encodes the transmitted message into a transmitted codeword from a channel code and transmits the transmitted codeword over a channel 120. The channel 120 produces a channel output in response to the transmitted codeword. In the split decoder apparatus 200, 400, a decode client 210, 410 receives the channel output 201 and generates a compressed error information 202, and a decode server 220, 420 receives the compressed error information 202 and generates a compressed error estimate 203. The decode client 210, 410 receives the compressed error estimate 203 and generates a message estimate 204. Communication complexity between the decode client 210, 410 and the decode server 220, 420 is reduced.