Split-Die Memory Circuit Layout for Bandwidth and Power Limits
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Solution Overview
Problem
Current memory devices struggle to fully exploit the benefits of advanced manufacturing technologies due to limitations in bandwidth, power consumption, and customization of memory capacity and I/O width, leading to suboptimal performance and higher power usage.
Innovation Solution
The solution involves separating the memory array and peripheral circuits into different dies, allowing for customized manufacturing processes and communication interfaces, enabling flexible I/O density and optimized power consumption by utilizing 2.5D or 3D IC packaging techniques such as interposers and die-to-die vias.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If memory array and peripheral circuits are integrated on the same die, then device complexity is reduced, but bandwidth and power consumption are suboptimal
Solution Approach 1:
The patent divides the memory device into separate dies: a first die containing the memory array and a second die containing peripheral circuits (address decoder, sense amplifiers, I/O interfaces). This segmentation allows each die to be independently optimized for its specific function, enabling higher bandwidth through dedicated high-speed interconnects while maintaining manageable device complexity through modular architecture.
Solution Approach 2:
The patent transitions from a two-dimensional integration approach to a three-dimensional stacked architecture using 2.5D or 3D IC packaging techniques. Multiple dies are stacked vertically and interconnected through through-silicon vias (TSVs) or micro-bumps, creating high-density interconnects that significantly increase bandwidth while keeping the footprint compact.
2Ease of manufacture
If memory array and peripheral circuits are integrated on the same die, then manufacturing process is simplified, but power consumption increases
Solution Approach 1:
By segmenting the memory device into separate functional dies, the patent enables independent manufacturing optimization. The memory array die can be fabricated using processes optimized for high-density storage, while the peripheral circuits die can use processes optimized for low-power logic operations. This reduces overall power consumption while the modular design simplifies manufacturing through specialized fabrication lines for each die type.
Solution Approach 2:
The patent applies different manufacturing process qualities to different parts of the system. The memory array die uses processes optimized for cell density and retention characteristics, while the peripheral circuits die uses processes optimized for switching speed and power efficiency. This local optimization of manufacturing quality reduces power consumption in critical areas without compromising overall device performance.
3Adaptability or versatility
If memory array and peripheral circuits are integrated on the same die, then I/O density is limited, but customization of memory capacity is reduced
Solution Approach 1:
The patent separates the memory array die from the peripheral circuits die, allowing independent scaling and customization. The memory array die can be configured with different capacities (e.g., 1Gb, 2Gb, 4Gb) while the peripheral circuits die maintains standardized I/O interfaces. This enables customization of memory capacity without increasing I/O density requirements, as the I/O functions are consolidated in the separate peripheral die.
Solution Approach 2:
The peripheral circuits die serves multiple functions: address decoding, data buffering, I/O interface control, and inter-die communication management. By consolidating these diverse functions in a single die, the patent achieves high I/O density while maintaining the ability to customize memory capacity in the separate array die. The universal peripheral die can support multiple memory capacity configurations.
Data Source
AI summary
A circuit is provided. The circuit includes a first die that includes a memory array, and the memory array includes a plurality of memory cells, a sensing element coupled to the plurality of memory cells, and a first plurality of conductive pads coupled to the sensing element. The circuit also includes a second die that includes an address decoder associated with the memory array of the first die and a second plurality of conductive pads coupled to the address decoder. The first die is coupled to the second die by an interposer. The address decoder of the second die is coupled to the sensing element of the first die. A first voltage swing of the first die is larger than a second voltage swing of the second die.