Split-Die SoC Register Mapping to Avoid EMIB-Crossing Latency
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Solution Overview
Problem
Split-die SoC designs suffer from increased transaction latencies due to Embedded Multi-Die Interconnect Bridge (EMIB) crossings, particularly in Non-Coherent (NC) transactions like Configuration Space Register (CSR) accesses, leading to prolonged DDR5 memory training times and platform cold boot times.
Innovation Solution
Implement a Pre-Memory Transient System Address Map that reconfigures the Ubox MMIO ranges for non-legacy sockets to be within their own Sub-NUMA Cluster, ensuring Core→CHA affinity and avoiding EMIB crossings during memory training.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If split-die SoC design is used to reduce manufacturing cost and improve scalability, then manufacturing cost and scalability are improved, but transaction latency increases due to EMIB crossings
Solution Approach 1:
The system is divided into multiple dielets (compute dielet, I/O dielet) connected via EMIB interconnect. This segmentation allows independent manufacturing and scaling of different functional blocks, reducing overall manufacturing cost while enabling flexible configuration. The segmentation principle resolves the contradiction by accepting the time penalty of inter-die communication in exchange for manufacturing benefits.
Solution Approach 2:
The EMIB (Embedded Multi-Die Interconnect Bridge) acts as an intermediary component that enables communication between separate dielets. This intermediary structure allows the system to maintain modularity and manufacturing advantages while providing a dedicated communication path that minimizes latency penalties compared to alternative interconnection methods.
2Adaptability or versatility
If Non-Coherent CSR transactions are used in split-die design, then system flexibility is improved, but access latency increases significantly
Solution Approach 1:
The system performs preliminary actions by establishing affinity rules and address map configurations before CSR transactions occur. The BIOS/UEFI firmware pre-configures the system to recognize which CSRs are local to which dielets, enabling faster access patterns to be established in advance, thereby reducing the latency impact of non-coherent transactions.
Solution Approach 2:
The patent implements local quality by allowing different access characteristics for different CSR regions. CSRs that are frequently accessed are placed in local address spaces on the same dielet as the cores, while less frequently accessed CSRs can reside on remote dielets. This creates locally optimized access paths for critical registers, reducing overall access latency while maintaining system flexibility.
3Manufacturing precision
If DDR5 memory training with high CSR access count is performed, then memory training accuracy is improved, but training time increases by 300-400%
Solution Approach 1:
The BIOS/UEFI firmware performs preliminary configuration of the address map and affinity rules before initiating memory training. This pre-configuration ensures that during the intensive CSR access phase of memory training, the system can efficiently route accesses to the appropriate dielets, minimizing latency overhead and reducing overall training time while maintaining accuracy.
Solution Approach 2:
The system dynamically adjusts access patterns during memory training by utilizing the affinity-based routing mechanism. As training progresses and access patterns become more predictable, the system can optimize routing decisions in real-time, reducing latency for repeated CSR accesses while maintaining the precision required for accurate memory training.
Data Source
AI summary
Methods and apparatus to reduce register access latency in split-die SoC designs. The method is implemented on a platform including a legacy socket and one or more non-legacy (NL) sockets comprising split-die System-on-Chips (SoC)s including multiple dielets interconnected with a plurality of Embedded Multi-Die Interconnect Bridges (EMIBs). The dielets include core dielets having cores, cache controllers and memory controllers. The method provides an affinity between a control and status registers (CSRs) memory range for the NL sockets such that CSRs in the memory controllers for multiple core dielets are programmed using transactions forwarded along core-to-cache controller datapaths that avoid crossing EMIBs. In one aspect, a transient map of address ranges is created that includes a respective Sub-NUMA Cluster (SNC) range allocated for the NL sockets, with a range of CSR addresses for accessing CSRs in the memory controllers for the NL sockets being stored in the respective SNC ranges.