Split Discharge Circuit Mitigates Snapback in Non-Volatile Memory
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Solution Overview
Problem
Conventional flash memory devices experience the undesirable phenomenon of snapback during the discharge of erase voltage, leading to high current between the source and drain regions of the discharge transistor, which can alter the performance of the memory device.
Innovation Solution
The charge pump and discharge circuitry is modified to split the discharge operation into two periods, using a pair of discharge transistors and an intermediate control voltage to prevent snapback, and a third discharge transistor to fully discharge the remaining voltage, ensuring the discharge transistor operates within a controlled region.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If a single discharge transistor is used to discharge the erase voltage quickly, then the discharge time is reduced, but snapback occurs causing high current between source and drain regions
Solution Approach 1:
The discharge operation is divided into two distinct phases: a first discharge phase using a first discharge transistor to discharge voltage to a first level, and a second discharge phase using a second discharge transistor to discharge the remaining voltage to ground. This segmentation prevents snapback by controlling the discharge rate and voltage levels at different stages.
Solution Approach 2:
The patent employs dynamic control of discharge transistors with different threshold voltages. The first discharge transistor has a first threshold voltage and the second has a second threshold voltage, allowing the discharge characteristics to change dynamically during operation. This enables the system to adapt the discharge rate based on the remaining voltage level, preventing snapback while maintaining efficient discharge.
2Productivity
If the discharge transistor is activated quickly to reduce discharge time, then productivity improves, but snapback occurs causing high current that may alter memory device performance
Solution Approach 1:
The discharge process is segmented into two stages with different transistors. The first stage uses a first discharge transistor activated when the control signal exceeds a first threshold, discharging voltage to a first level. The second stage uses a second discharge transistor activated when the control signal exceeds a second threshold, completing the discharge to ground. This segmentation allows controlled activation that prevents harmful snapback current while maintaining discharge speed.
Solution Approach 2:
The patent implements dynamic transistor activation based on the control signal level. The first discharge transistor activates at a lower threshold voltage level, while the second discharge transistor activates at a higher threshold voltage level. This dynamic activation strategy ensures that transistors are turned on at appropriate moments during discharge, preventing snapback while maintaining high discharge productivity.
3Device complexity
If a single discharge transistor is used, then device complexity is reduced, but the discharge transistor must operate across a wide voltage range increasing susceptibility to snapback
Solution Approach 1:
The discharge circuit is segmented into two parallel paths, each with its own discharge transistor. The first discharge transistor handles the initial discharge to a first voltage level, while the second discharge transistor handles the final discharge to ground. This segmentation distributes the voltage range handling across multiple devices, reducing snapback susceptibility in each individual transistor while maintaining manageable circuit complexity.
Data Source
AI summary
Charge pump and discharge circuitry for a non-volatile memory device that splits up the discharge operation into two discharge periods. In a first discharge period, the voltage being discharged (e.g., erase voltage) is discharged through a pair of discharge transistors until the discharging voltage reaches a first voltage level. The path through the pair of discharge transistors is controlled by an intermediate control voltage so that none of the transistors of the pair enter the snapback condition. In the second discharge period, the remaining discharging voltage is fully discharged from the first level through a third discharge transistor.