Split Display Driven by Dual Pipelines and VBI Sync
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Solution Overview
Problem
Existing display pipelines struggle to support high resolution displays and high frame refresh rates, leading to inadequate pixel processing and potential artifacts in video streams.
Innovation Solution
Implementing two display pipelines with a master timing generator, where each pipeline processes half of the image frame, using FIFO buffers and control units to manage frame packets and generate vertical blanking interval signals for synchronized processing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a single display pipeline is used to drive high resolution displays, then the system structure remains simple, but the pixel processing capability becomes insufficient
Solution Approach 1:
The display pipeline is segmented into multiple independent pipelines, where each pipeline processes a specific portion of the display resolution. For example, in a dual-pipeline configuration, each pipeline handles half of the total pixel bandwidth, thereby increasing overall processing capability while maintaining manageable complexity through modular design.
2Speed
If the frame refresh rate is increased to 120 Hz or higher, then the display smoothness is improved, but the processing load on the display pipeline increases significantly
Solution Approach 1:
The processing load is segmented across multiple display pipelines operating in parallel. Each pipeline handles a portion of the frame data at the high refresh rate, distributing the computational burden and enabling sustained high frame rates without overwhelming a single processing unit.
Solution Approach 2:
Frame data is pre-processed and prepared in advance using techniques such as frame buffering and double buffering. This preliminary action allows the display pipeline to smoothly transition between frames at high refresh rates without processing bottlenecks, as data is ready for immediate display when needed.
3Productivity
If multiple display pipelines are used to process frame portions, then the pixel processing capability is sufficient for high resolution displays, but the synchronization between pipelines becomes complex
Solution Approach 1:
A master timing generator provides centralized feedback control to multiple display pipelines, distributing synchronized timing signals that coordinate frame processing across all pipelines. This feedback mechanism ensures that each pipeline processes its assigned frame portion in sync with the others, maintaining image coherence without requiring complex peer-to-peer synchronization protocols.
4Reliability
If a single display pipeline processes the entire frame, then the system is easier to control, but artifacts may appear in video streams due to inadequate processing
Solution Approach 1:
The display pipeline is segmented into multiple independent processing units, each handling a specific portion of the frame. This segmentation increases overall processing capability and reduces artifacts in video streams, as each pipeline can be optimized for its specific workload while collectively maintaining high image quality across the entire display.
Data Source
AI summary
Systems, apparatuses, and methods for driving a split display with multiple display pipelines. Frames for driving a display are logically divided into portions, a first display pipeline drives a first portion of the display, and a second display pipeline drives a second portion of the display. To ensure synchronization between the two display pipelines, a repeat vertical blanking interval (VBI) signal is generated if either of the display pipelines has not already received the frame packet with configuration data for the next frame. When the repeat VBI signal is generated, both display pipelines will repeat processing of the current frame.