Split Cross-Coupled Frequency Divider Latch Against Lock-Up
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Solution Overview
Problem
High-speed pseudo-differential frequency divider circuits are prone to lock-up due to unwanted common-mode operation, which leads to failure and increased power consumption.
Innovation Solution
The implementation of split cross-coupled pseudo-differential frequency divider circuits, which replace the pseudo-differential latch with a split cross-coupled pseudo-differential latch, prevents common-mode signal propagation to subsequent latches, thereby reducing or eliminating lock-up.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If pseudo-differential latch is used in frequency divider circuit, then circuit complexity is reduced, but common-mode operation occurs causing lock-up
Solution Approach 1:
The pseudo-differential latch is segmented into separate differential paths with independent control. The frequency divider circuit is divided into multiple stages where each stage has its own differential pair and control logic, preventing common-mode signals from propagating through the entire latch structure simultaneously.
Solution Approach 2:
Control gates are introduced as intermediary elements between the differential inputs and the latch outputs. These gates act as mediators that selectively block or pass signals based on control conditions, preventing unwanted common-mode operation while maintaining differential signal integrity.
2Productivity
If high-speed operation is implemented, then productivity is improved, but common-mode operation and lock-up increase
Solution Approach 1:
The circuit employs dynamic control gates that switch states based on clock phases and control signals. This dynamic behavior allows the circuit to maintain high-speed operation while adaptively preventing common-mode lock-up conditions that arise at higher frequencies.
Solution Approach 2:
The frequency divider uses periodic clock signals to control the timing of signal propagation through different stages. By synchronizing control gate activation with clock edges, the circuit maintains high-speed periodic operation while preventing common-mode signals from causing lock-up during critical transition periods.
3Ease of operation
If common-mode operation is allowed, then ease of operation is improved, but power consumption increases
Solution Approach 1:
The unwanted common-mode operation is extracted and separated from the desired differential operation. Control gates are configured to extract and block common-mode signals while allowing differential signals to pass, preventing the energy-wasting lock-up condition while maintaining ease of differential circuit operation.
Data Source
AI summary
An example apparatus includes: first through eighth gated inverters each having inputs and outputs; a first and second inverter each having an input and an output, the output of the first inverter coupled to the input of the second gated inverter, the output of the second inverter coupled to the input of the third gated inverter; the fifth gated inverter coupled to the input of the first gated inverter and the input of the first inverter; the sixth gated inverter coupled to the input of the second inverter and the input of the fourth gated inverter; the seventh gated inverter coupled to the output of the first gated inverter and the output of the third gated inverter; the eighth gated inverter coupled to the output of the second gated inverter and the output of the fourth gated inverter; and a bus-holder circuit between the seventh and eighth gated inverter inputs.