Split DMA Descriptor Control for Secure Memory Transfers
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Solution Overview
Problem
Implementing direct memory access (DMA) transfer operations is complex, particularly due to security concerns related to DMA software drivers needing knowledge of the memory spaces of involved devices, which poses risks and inefficiencies.
Innovation Solution
The method involves configuring and managing DMA engines by separating descriptor control between host and endpoint devices, using shared status indicators to coordinate DMA operations and maintain independent coalesce count controls, thereby keeping each device unaware of the other's addressing and reducing security risks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If DMA software drivers require knowledge of the memory spaces of the devices involved in DMA transfer operations, then the DMA operations can be properly configured and executed, but security risks increase and system complexity increases
Solution Approach 1:
The patent segments the DMA control into two independent parts: host descriptors managed by the host driver and endpoint descriptors managed by the endpoint driver. Each driver only needs to know its own device's memory space, not the other device's memory space. This segmentation maintains DMA operation correctness while reducing security risks by limiting memory space knowledge to only what is necessary for each driver.
Solution Approach 2:
The patent introduces an intermediary mechanism where the DMA engine acts as a mediator between the host and endpoint devices. The host driver configures host descriptors and the endpoint driver configures endpoint descriptors, with the DMA engine coordinating their interaction without requiring either driver to directly access or know the other's memory space, thus reducing security risks while maintaining operational correctness.
2Reliability
If DMA software drivers require knowledge of the memory spaces of the devices involved in DMA transfer operations, then the DMA operations can be properly configured and executed, but device complexity increases
Solution Approach 1:
The patent segments the complex DMA configuration task into two simpler, independent sub-tasks: configuring host descriptors and configuring endpoint descriptors. Each driver only handles its own segment, reducing the complexity of individual drivers while maintaining the overall correctness of DMA operations through the coordinated interaction of both segments.
Solution Approach 2:
Each driver (host driver and endpoint driver) independently configures its own descriptors without requiring complex knowledge of the other driver's memory space or configuration details. This self-service approach simplifies driver implementation while the DMA engine ensures proper coordination, reducing overall system complexity.
3Reliability
If one driver needs to access the other's memory space for DMA operations, then coordinated control can be achieved, but security risks increase
Solution Approach 1:
The patent uses the DMA engine as an intermediary that enables coordinated control between host and endpoint devices without requiring direct memory space access between drivers. The host driver writes host descriptors to host memory, the endpoint driver writes endpoint descriptors to endpoint memory, and the DMA engine coordinates their interaction, achieving reliable DMA coordination while preventing direct memory space access that would create security risks.
Solution Approach 2:
The patent segments memory access permissions so that the host driver only accesses host memory space and the endpoint driver only accesses endpoint memory space. This segmentation eliminates the need for cross-memory-space access while maintaining coordinated control through the DMA engine, thereby reducing security risks.
Data Source
AI summary
A signature is generated to indicate a direct memory access (DMA) operation involving a transfer, by a DMA engine, of data between a host memory circuit and an endpoint memory circuit of an endpoint processor circuit. First descriptors of the DMA engine are defined relative to the endpoint memory circuit or host memory circuit. A signature is received that indicates that second descriptors have been configured by the endpoint processor circuit. In response to receiving the endpoint signature, the DMA engine is enabled to begin the DMA operation.