Split Double Gate Transistor Structure for Back-Bias Voltage Control
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Solution Overview
Problem
Conventional Gate-All-Around (GAA) architectures face challenges in process variations leading to inconsistent carrier mobility, threshold voltages, and lack of back gates for dynamic voltage control, affecting yield and performance in stacked nanowire and nanosheet transistors.
Innovation Solution
A method for manufacturing a split double gate transistor involves forming a fin with alternating gate metal and sacrificial layers, patterning and filling recesses with spacers, and creating separate gate components to accommodate back gates, ensuring consistent channel layer formation and improved electrostatic control.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional GAA architecture with fully surrounded channels is used, then electrostatic control and short channel effects are improved, but back gates cannot be accommodated for dynamic voltage control
Solution Approach 1:
The gate structure is segmented into front gate and back gate components, allowing independent control of channel regions. The channel layer is divided into first and second portions with different gate controls, enabling both electrostatic control and back-biasing functionality simultaneously
Solution Approach 2:
The design transitions from a conventional single-gate architecture to a split double gate architecture by adding the back gate dimension. This allows voltage control from both the front and back of the channel, providing flexible tuning of threshold voltages while maintaining electrostatic control
2Productivity
If sequential epitaxial growth of stacked channel layers is used, then transistor stacking is achieved, but process variations cause inconsistent thickness, crystal quality, and doping concentration
Solution Approach 1:
The sacrificial layers are formed with precise thickness control before channel layer deposition. This preliminary structuring allows subsequent channel layers to be deposited with better process control and reduced variations in thickness and doping concentration
Solution Approach 2:
Sacrificial layers serve as intermediaries during fabrication, enabling precise positioning and spacing of channel layers. These sacrificial structures facilitate controlled deposition processes and ensure consistent channel layer formation while maintaining stacking productivity
3Device complexity
If sequential multi-stage fabrication process is used, then stacked transistor structure is formed, but temperature fluctuations and gas flow changes lead to performance unpredictability
Solution Approach 1:
The fabrication process utilizes precise control of deposition parameters including temperature, gas flow, and material supply rates. By optimizing and stabilizing these parameters throughout the sequential process, consistent channel layer properties are achieved despite the complexity of multiple fabrication stages
Data Source
AI summary
A method for manufacturing a split double gate transistor includes: forming a first fin on a substrate; removing sacrificial layers from a portion of the first fin; sequentially forming a first gate insulating layer, a channel layer and a protection layer on exposed portions of each gate metal layer; performing a patterning process to form a second fin; patterning the second fin to form a plurality of first recesses and a plurality of second recesses; forming a plurality of inner spacer layers; forming a first gate component, a drain component and a source component; removing the protection layer; and sequentially forming a second gate insulating layer, a plurality of gate connectors, and a second gate component.